Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / ticket92 / cover_report1.vhd @ 3fd18385

History | View | Annotate | Download (929 Bytes)

1
library ieee;
2
  use ieee.std_logic_1164.all;
3

    
4
library std;
5
  use std.env.all;
6

    
7

    
8

    
9
entity cover_report1 is
10
end entity cover_report1;
11

    
12
architecture test of cover_report1 is
13

    
14

    
15
  signal s_a   : std_logic;
16
  signal s_b   : std_logic;
17
  signal s_c   : std_logic;
18
  signal s_clk : std_logic := '0';
19

    
20

    
21
begin
22

    
23

    
24
  s_clk <= not(s_clk) after 5 ns;
25

    
26

    
27
  process is
28
  begin
29
    s_a <= '0';
30
    s_b <= '0';
31
    s_c <= '0';
32
    wait until rising_edge(s_clk);
33
    s_a <= '1';
34
    wait until rising_edge(s_clk);
35
    s_a <= '0';
36
    --s_b <= '1';
37
    wait until rising_edge(s_clk);
38
    s_b <= '0';
39
    wait until rising_edge(s_clk);
40
    s_c <= '0';
41
    stop(0);
42
  end process;
43

    
44

    
45
  -- psl default clock is rising_edge(s_clk);
46
  --
47
  -- psl sequence test_p is {s_a; s_b};
48
  --
49
  -- DOES WORK
50
  -- -- psl TEST : cover test_p;
51
  --
52
  -- DOESN'T WORK:
53
  -- psl cover test_p report "Covered";
54
  -- - psl assert eventually! test_p;
55

    
56

    
57
end architecture test;