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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / sr2553 / 2553.json @ 3fd18385

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "e1"], "ports" : [{
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          "names" : [["IDENTIFIER", "r1"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "real"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "slv1"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "7"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "sl1"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "a"], "entity" : ["IDENTIFIER", "e1"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "e2"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "a"], "entity" : ["IDENTIFIER", "e2"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["CONSTANT_DECLARATION", {
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            "names" : [["IDENTIFIER", "r2"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "integer"]}
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            , "init_val" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "10"], "unit_name" : ["SIMPLE_NAME", "e6"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "slv2"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                "ranges" : [["RANGE_WITH_DIRECTION", {
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                  "direction" : "downto", "from" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "7"]}
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                      ]]}
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                    ]]}
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                  ], "_to" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "0"]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]]}
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              ]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "sl2"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "tx"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "e1"]]], "inst_unit_type" : "entity", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "r1"], "actual_designator" : ["INDEXED_NAME", {
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              "id" : ["SIMPLE_NAME", "real"], "exprs" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "r2_wrong"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "slv1"], "actual_designator" : ["SIMPLE_NAME", "slv2"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "sl1"], "actual_designator" : ["SIMPLE_NAME", "sl2"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }