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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue50 / vector.d / top.vhd @ 3fd18385

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1
library ieee;
2
use ieee.std_logic_1164.all;
3

    
4
entity top is
5
	port (
6
		clock : in  std_logic;
7
		reset : in  std_logic;
8
		start : in  std_logic;
9
		stdin_data : in  std_logic_vector(31 downto 0);
10
		stdin_rdy : out std_logic;
11
		stdin_ack : in  std_logic;
12
		stdout_data : out std_logic_vector(31 downto 0);
13
		stdout_rdy : out std_logic;
14
		stdout_ack : in  std_logic;
15
		cp_en : in  std_logic;
16
		cp_rest : in  std_logic;
17
		cp_din : in  std_logic_vector(63 downto 0);
18
		cp_dout : out std_logic_vector(63 downto 0);
19
		cp_ok : out std_logic
20
	);
21
end top;
22

    
23
architecture augh of top is
24

    
25
	-- Declaration of components
26

    
27
	component v_split0 is
28
		port (
29
			clk : in  std_logic;
30
			ra0_data : out std_logic_vector(7 downto 0);
31
			wa0_data : in  std_logic_vector(7 downto 0);
32
			wa0_addr : in  std_logic;
33
			wa0_en : in  std_logic;
34
			ra0_addr : in  std_logic
35
		);
36
	end component;
37

    
38
	component v_split1 is
39
		port (
40
			clk : in  std_logic;
41
			ra0_data : out std_logic_vector(7 downto 0);
42
			wa0_data : in  std_logic_vector(7 downto 0);
43
			wa0_addr : in  std_logic;
44
			wa0_en : in  std_logic;
45
			ra0_addr : in  std_logic
46
		);
47
	end component;
48

    
49
	component v_split2 is
50
		port (
51
			clk : in  std_logic;
52
			ra0_data : out std_logic_vector(7 downto 0);
53
			wa0_data : in  std_logic_vector(7 downto 0);
54
			wa0_addr : in  std_logic;
55
			wa0_en : in  std_logic;
56
			ra0_addr : in  std_logic
57
		);
58
	end component;
59

    
60
	component v_split3 is
61
		port (
62
			clk : in  std_logic;
63
			ra0_data : out std_logic_vector(7 downto 0);
64
			wa0_data : in  std_logic_vector(7 downto 0);
65
			wa0_addr : in  std_logic;
66
			wa0_en : in  std_logic;
67
			ra0_addr : in  std_logic
68
		);
69
	end component;
70

    
71
	component v_split4 is
72
		port (
73
			clk : in  std_logic;
74
			ra0_data : out std_logic_vector(7 downto 0);
75
			wa0_data : in  std_logic_vector(7 downto 0);
76
			wa0_addr : in  std_logic;
77
			wa0_en : in  std_logic;
78
			ra0_addr : in  std_logic
79
		);
80
	end component;
81

    
82
	component v_split5 is
83
		port (
84
			clk : in  std_logic;
85
			ra0_data : out std_logic_vector(7 downto 0);
86
			wa0_data : in  std_logic_vector(7 downto 0);
87
			wa0_addr : in  std_logic;
88
			wa0_en : in  std_logic;
89
			ra0_addr : in  std_logic
90
		);
91
	end component;
92

    
93
	component v_split6 is
94
		port (
95
			clk : in  std_logic;
96
			ra0_data : out std_logic_vector(7 downto 0);
97
			wa0_data : in  std_logic_vector(7 downto 0);
98
			wa0_addr : in  std_logic;
99
			wa0_en : in  std_logic;
100
			ra0_addr : in  std_logic
101
		);
102
	end component;
103

    
104
	component v_split7 is
105
		port (
106
			clk : in  std_logic;
107
			ra0_data : out std_logic_vector(7 downto 0);
108
			wa0_data : in  std_logic_vector(7 downto 0);
109
			wa0_addr : in  std_logic;
110
			wa0_en : in  std_logic;
111
			ra0_addr : in  std_logic
112
		);
113
	end component;
114

    
115
	component w_split0 is
116
		port (
117
			clk : in  std_logic;
118
			ra0_data : out std_logic_vector(7 downto 0);
119
			wa0_data : in  std_logic_vector(7 downto 0);
120
			wa0_addr : in  std_logic;
121
			wa0_en : in  std_logic;
122
			ra0_addr : in  std_logic
123
		);
124
	end component;
125

    
126
	component w_split1 is
127
		port (
128
			clk : in  std_logic;
129
			ra0_data : out std_logic_vector(7 downto 0);
130
			wa0_data : in  std_logic_vector(7 downto 0);
131
			wa0_addr : in  std_logic;
132
			wa0_en : in  std_logic;
133
			ra0_addr : in  std_logic
134
		);
135
	end component;
136

    
137
	component w_split2 is
138
		port (
139
			clk : in  std_logic;
140
			ra0_data : out std_logic_vector(7 downto 0);
141
			wa0_data : in  std_logic_vector(7 downto 0);
142
			wa0_addr : in  std_logic;
143
			wa0_en : in  std_logic;
144
			ra0_addr : in  std_logic
145
		);
146
	end component;
147

    
148
	component w_split3 is
149
		port (
150
			clk : in  std_logic;
151
			ra0_data : out std_logic_vector(7 downto 0);
152
			wa0_data : in  std_logic_vector(7 downto 0);
153
			wa0_addr : in  std_logic;
154
			wa0_en : in  std_logic;
155
			ra0_addr : in  std_logic
156
		);
157
	end component;
158

    
159
	component w_split4 is
160
		port (
161
			clk : in  std_logic;
162
			ra0_data : out std_logic_vector(7 downto 0);
163
			wa0_data : in  std_logic_vector(7 downto 0);
164
			wa0_addr : in  std_logic;
165
			wa0_en : in  std_logic;
166
			ra0_addr : in  std_logic
167
		);
168
	end component;
169

    
170
	component w_split5 is
171
		port (
172
			clk : in  std_logic;
173
			ra0_data : out std_logic_vector(7 downto 0);
174
			wa0_data : in  std_logic_vector(7 downto 0);
175
			wa0_addr : in  std_logic;
176
			wa0_en : in  std_logic;
177
			ra0_addr : in  std_logic
178
		);
179
	end component;
180

    
181
	component w_split6 is
182
		port (
183
			clk : in  std_logic;
184
			ra0_data : out std_logic_vector(7 downto 0);
185
			wa0_data : in  std_logic_vector(7 downto 0);
186
			wa0_addr : in  std_logic;
187
			wa0_en : in  std_logic;
188
			ra0_addr : in  std_logic
189
		);
190
	end component;
191

    
192
	component w_split7 is
193
		port (
194
			clk : in  std_logic;
195
			ra0_data : out std_logic_vector(7 downto 0);
196
			wa0_data : in  std_logic_vector(7 downto 0);
197
			wa0_addr : in  std_logic;
198
			wa0_en : in  std_logic;
199
			ra0_addr : in  std_logic
200
		);
201
	end component;
202

    
203
	component add_171 is
204
		port (
205
			result : out std_logic_vector(31 downto 0);
206
			in_a : in  std_logic_vector(31 downto 0);
207
			in_b : in  std_logic_vector(31 downto 0)
208
		);
209
	end component;
210

    
211
	component cmp_183 is
212
		port (
213
			eq : out std_logic;
214
			in0 : in  std_logic_vector(2 downto 0);
215
			in1 : in  std_logic_vector(2 downto 0)
216
		);
217
	end component;
218

    
219
	component cmp_185 is
220
		port (
221
			eq : out std_logic;
222
			in0 : in  std_logic_vector(2 downto 0);
223
			in1 : in  std_logic_vector(2 downto 0)
224
		);
225
	end component;
226

    
227
	component cmp_193 is
228
		port (
229
			eq : out std_logic;
230
			in0 : in  std_logic_vector(2 downto 0);
231
			in1 : in  std_logic_vector(2 downto 0)
232
		);
233
	end component;
234

    
235
	component cmp_195 is
236
		port (
237
			eq : out std_logic;
238
			in0 : in  std_logic_vector(2 downto 0);
239
			in1 : in  std_logic_vector(2 downto 0)
240
		);
241
	end component;
242

    
243
	component muxb_120 is
244
		port (
245
			in_sel : in  std_logic;
246
			out_data : out std_logic;
247
			in_data0 : in  std_logic;
248
			in_data1 : in  std_logic
249
		);
250
	end component;
251

    
252
	component muxb_124 is
253
		port (
254
			in_sel : in  std_logic;
255
			out_data : out std_logic;
256
			in_data0 : in  std_logic;
257
			in_data1 : in  std_logic
258
		);
259
	end component;
260

    
261
	component cmp_128 is
262
		port (
263
			eq : out std_logic;
264
			in0 : in  std_logic_vector(2 downto 0);
265
			in1 : in  std_logic_vector(2 downto 0)
266
		);
267
	end component;
268

    
269
	component cmp_130 is
270
		port (
271
			eq : out std_logic;
272
			in0 : in  std_logic_vector(2 downto 0);
273
			in1 : in  std_logic_vector(2 downto 0)
274
		);
275
	end component;
276

    
277
	component cmp_132 is
278
		port (
279
			eq : out std_logic;
280
			in0 : in  std_logic_vector(2 downto 0);
281
			in1 : in  std_logic_vector(2 downto 0)
282
		);
283
	end component;
284

    
285
	component cmp_136 is
286
		port (
287
			eq : out std_logic;
288
			in0 : in  std_logic_vector(2 downto 0);
289
			in1 : in  std_logic_vector(2 downto 0)
290
		);
291
	end component;
292

    
293
	component cmp_137 is
294
		port (
295
			eq : out std_logic;
296
			in0 : in  std_logic_vector(2 downto 0);
297
			in1 : in  std_logic_vector(2 downto 0)
298
		);
299
	end component;
300

    
301
	component cmp_138 is
302
		port (
303
			eq : out std_logic;
304
			in0 : in  std_logic_vector(2 downto 0);
305
			in1 : in  std_logic_vector(2 downto 0)
306
		);
307
	end component;
308

    
309
	component cmp_139 is
310
		port (
311
			eq : out std_logic;
312
			in0 : in  std_logic_vector(2 downto 0);
313
			in1 : in  std_logic_vector(2 downto 0)
314
		);
315
	end component;
316

    
317
	component cmp_140 is
318
		port (
319
			eq : out std_logic;
320
			in0 : in  std_logic_vector(2 downto 0);
321
			in1 : in  std_logic_vector(2 downto 0)
322
		);
323
	end component;
324

    
325
	component cmp_141 is
326
		port (
327
			eq : out std_logic;
328
			in0 : in  std_logic_vector(2 downto 0);
329
			in1 : in  std_logic_vector(2 downto 0)
330
		);
331
	end component;
332

    
333
	component cmp_142 is
334
		port (
335
			eq : out std_logic;
336
			in0 : in  std_logic_vector(2 downto 0);
337
			in1 : in  std_logic_vector(2 downto 0)
338
		);
339
	end component;
340

    
341
	component muxb_117 is
342
		port (
343
			in_sel : in  std_logic;
344
			out_data : out std_logic;
345
			in_data0 : in  std_logic;
346
			in_data1 : in  std_logic
347
		);
348
	end component;
349

    
350
	component add_118 is
351
		port (
352
			result : out std_logic_vector(15 downto 0);
353
			in_a : in  std_logic_vector(15 downto 0);
354
			in_b : in  std_logic_vector(15 downto 0)
355
		);
356
	end component;
357

    
358
	component cmp_119 is
359
		port (
360
			ne : out std_logic;
361
			in0 : in  std_logic_vector(15 downto 0);
362
			in1 : in  std_logic_vector(15 downto 0)
363
		);
364
	end component;
365

    
366
	component muxb_121 is
367
		port (
368
			in_sel : in  std_logic;
369
			out_data : out std_logic;
370
			in_data0 : in  std_logic;
371
			in_data1 : in  std_logic
372
		);
373
	end component;
374

    
375
	component muxb_123 is
376
		port (
377
			in_sel : in  std_logic;
378
			out_data : out std_logic;
379
			in_data0 : in  std_logic;
380
			in_data1 : in  std_logic
381
		);
382
	end component;
383

    
384
	component sub_125 is
385
		port (
386
			le : out std_logic;
387
			sign : in  std_logic;
388
			result : out std_logic_vector(31 downto 0);
389
			in_a : in  std_logic_vector(31 downto 0);
390
			in_b : in  std_logic_vector(31 downto 0)
391
		);
392
	end component;
393

    
394
	component cmp_126 is
395
		port (
396
			eq : out std_logic;
397
			in0 : in  std_logic_vector(2 downto 0);
398
			in1 : in  std_logic_vector(2 downto 0)
399
		);
400
	end component;
401

    
402
	component add_134 is
403
		port (
404
			result : out std_logic_vector(31 downto 0);
405
			in_a : in  std_logic_vector(31 downto 0);
406
			in_b : in  std_logic_vector(31 downto 0)
407
		);
408
	end component;
409

    
410
	component sub_145 is
411
		port (
412
			result : out std_logic_vector(3 downto 0);
413
			in_a : in  std_logic_vector(3 downto 0);
414
			in_b : in  std_logic_vector(3 downto 0)
415
		);
416
	end component;
417

    
418
	component cmp_146 is
419
		port (
420
			eq : out std_logic;
421
			in0 : in  std_logic_vector(2 downto 0);
422
			in1 : in  std_logic_vector(2 downto 0)
423
		);
424
	end component;
425

    
426
	component add_170 is
427
		port (
428
			result : out std_logic_vector(8 downto 0);
429
			in_a : in  std_logic_vector(8 downto 0);
430
			in_b : in  std_logic_vector(8 downto 0)
431
		);
432
	end component;
433

    
434
	component cmp_174 is
435
		port (
436
			eq : out std_logic;
437
			in0 : in  std_logic_vector(2 downto 0);
438
			in1 : in  std_logic_vector(2 downto 0)
439
		);
440
	end component;
441

    
442
	component cmp_176 is
443
		port (
444
			eq : out std_logic;
445
			in0 : in  std_logic_vector(2 downto 0);
446
			in1 : in  std_logic_vector(2 downto 0)
447
		);
448
	end component;
449

    
450
	component cmp_178 is
451
		port (
452
			eq : out std_logic;
453
			in0 : in  std_logic_vector(2 downto 0);
454
			in1 : in  std_logic_vector(2 downto 0)
455
		);
456
	end component;
457

    
458
	component cmp_180 is
459
		port (
460
			eq : out std_logic;
461
			in0 : in  std_logic_vector(2 downto 0);
462
			in1 : in  std_logic_vector(2 downto 0)
463
		);
464
	end component;
465

    
466
	component cmp_187 is
467
		port (
468
			eq : out std_logic;
469
			in0 : in  std_logic_vector(2 downto 0);
470
			in1 : in  std_logic_vector(2 downto 0)
471
		);
472
	end component;
473

    
474
	component add_188 is
475
		port (
476
			result : out std_logic_vector(31 downto 0);
477
			in_a : in  std_logic_vector(31 downto 0);
478
			in_b : in  std_logic_vector(31 downto 0)
479
		);
480
	end component;
481

    
482
	component sub_189 is
483
		port (
484
			lt : out std_logic;
485
			sign : in  std_logic;
486
			result : out std_logic_vector(31 downto 0);
487
			in_a : in  std_logic_vector(31 downto 0);
488
			in_b : in  std_logic_vector(31 downto 0)
489
		);
490
	end component;
491

    
492
	component cmp_191 is
493
		port (
494
			eq : out std_logic;
495
			in0 : in  std_logic_vector(2 downto 0);
496
			in1 : in  std_logic_vector(2 downto 0)
497
		);
498
	end component;
499

    
500
	component cmp_198 is
501
		port (
502
			eq : out std_logic;
503
			in0 : in  std_logic_vector(2 downto 0);
504
			in1 : in  std_logic_vector(2 downto 0)
505
		);
506
	end component;
507

    
508
	component cmp_200 is
509
		port (
510
			eq : out std_logic;
511
			in0 : in  std_logic_vector(2 downto 0);
512
			in1 : in  std_logic_vector(2 downto 0)
513
		);
514
	end component;
515

    
516
	component cmp_202 is
517
		port (
518
			eq : out std_logic;
519
			in0 : in  std_logic_vector(2 downto 0);
520
			in1 : in  std_logic_vector(2 downto 0)
521
		);
522
	end component;
523

    
524
	component cmp_204 is
525
		port (
526
			eq : out std_logic;
527
			in0 : in  std_logic_vector(2 downto 0);
528
			in1 : in  std_logic_vector(2 downto 0)
529
		);
530
	end component;
531

    
532
	component add_214 is
533
		port (
534
			result : out std_logic_vector(7 downto 0);
535
			in_a : in  std_logic_vector(7 downto 0);
536
			in_b : in  std_logic_vector(7 downto 0)
537
		);
538
	end component;
539

    
540
	component cmp_215 is
541
		port (
542
			eq : out std_logic;
543
			in0 : in  std_logic_vector(2 downto 0);
544
			in1 : in  std_logic_vector(2 downto 0)
545
		);
546
	end component;
547

    
548
	component muxb_219 is
549
		port (
550
			in_sel : in  std_logic;
551
			out_data : out std_logic;
552
			in_data0 : in  std_logic;
553
			in_data1 : in  std_logic
554
		);
555
	end component;
556

    
557
	component add_220 is
558
		port (
559
			result : out std_logic_vector(15 downto 0);
560
			in_a : in  std_logic_vector(15 downto 0);
561
			in_b : in  std_logic_vector(15 downto 0)
562
		);
563
	end component;
564

    
565
	component cmp_221 is
566
		port (
567
			ne : out std_logic;
568
			in0 : in  std_logic_vector(15 downto 0);
569
			in1 : in  std_logic_vector(15 downto 0)
570
		);
571
	end component;
572

    
573
	component cmp_111 is
574
		port (
575
			eq : out std_logic;
576
			in0 : in  std_logic_vector(2 downto 0);
577
			in1 : in  std_logic_vector(2 downto 0)
578
		);
579
	end component;
580

    
581
	component cmp_113 is
582
		port (
583
			eq : out std_logic;
584
			in0 : in  std_logic_vector(2 downto 0);
585
			in1 : in  std_logic_vector(2 downto 0)
586
		);
587
	end component;
588

    
589
	component cmp_216 is
590
		port (
591
			eq : out std_logic;
592
			in0 : in  std_logic_vector(2 downto 0);
593
			in1 : in  std_logic_vector(2 downto 0)
594
		);
595
	end component;
596

    
597
	component cmp_217 is
598
		port (
599
			eq : out std_logic;
600
			in0 : in  std_logic_vector(2 downto 0);
601
			in1 : in  std_logic_vector(2 downto 0)
602
		);
603
	end component;
604

    
605
	component cmp_218 is
606
		port (
607
			eq : out std_logic;
608
			in0 : in  std_logic_vector(2 downto 0);
609
			in1 : in  std_logic_vector(2 downto 0)
610
		);
611
	end component;
612

    
613
	component fsm_15 is
614
		port (
615
			clock : in  std_logic;
616
			reset : in  std_logic;
617
			out3 : out std_logic;
618
			out157 : out std_logic;
619
			out159 : out std_logic;
620
			out160 : out std_logic;
621
			out171 : out std_logic;
622
			out172 : out std_logic;
623
			out173 : out std_logic;
624
			out175 : out std_logic;
625
			out178 : out std_logic;
626
			in0 : in  std_logic;
627
			out0 : out std_logic;
628
			in5 : in  std_logic;
629
			in6 : in  std_logic;
630
			in7 : in  std_logic;
631
			out35 : out std_logic;
632
			out39 : out std_logic;
633
			out40 : out std_logic;
634
			out41 : out std_logic;
635
			out44 : out std_logic;
636
			out46 : out std_logic;
637
			out140 : out std_logic;
638
			in8 : in  std_logic;
639
			in9 : in  std_logic;
640
			in10 : in  std_logic;
641
			in11 : in  std_logic;
642
			in12 : in  std_logic;
643
			in13 : in  std_logic;
644
			in14 : in  std_logic;
645
			out65 : out std_logic;
646
			in1 : in  std_logic;
647
			in2 : in  std_logic;
648
			in3 : in  std_logic;
649
			in4 : in  std_logic;
650
			out225 : out std_logic;
651
			out227 : out std_logic;
652
			out231 : out std_logic;
653
			out235 : out std_logic;
654
			out236 : out std_logic;
655
			out237 : out std_logic;
656
			out238 : out std_logic;
657
			out97 : out std_logic;
658
			out98 : out std_logic;
659
			out101 : out std_logic;
660
			out102 : out std_logic;
661
			out124 : out std_logic;
662
			out125 : out std_logic;
663
			out80 : out std_logic;
664
			out81 : out std_logic;
665
			out84 : out std_logic;
666
			out86 : out std_logic;
667
			out88 : out std_logic;
668
			out93 : out std_logic;
669
			out94 : out std_logic
670
		);
671
	end component;
672

    
673
	component cmp_112 is
674
		port (
675
			eq : out std_logic;
676
			in0 : in  std_logic_vector(2 downto 0);
677
			in1 : in  std_logic_vector(2 downto 0)
678
		);
679
	end component;
680

    
681
	component cmp_114 is
682
		port (
683
			eq : out std_logic;
684
			in0 : in  std_logic_vector(2 downto 0);
685
			in1 : in  std_logic_vector(2 downto 0)
686
		);
687
	end component;
688

    
689
	component cmp_115 is
690
		port (
691
			eq : out std_logic;
692
			in0 : in  std_logic_vector(2 downto 0);
693
			in1 : in  std_logic_vector(2 downto 0)
694
		);
695
	end component;
696

    
697
	component cmp_148 is
698
		port (
699
			eq : out std_logic;
700
			in0 : in  std_logic_vector(2 downto 0);
701
			in1 : in  std_logic_vector(2 downto 0)
702
		);
703
	end component;
704

    
705
	component cmp_150 is
706
		port (
707
			eq : out std_logic;
708
			in0 : in  std_logic_vector(2 downto 0);
709
			in1 : in  std_logic_vector(2 downto 0)
710
		);
711
	end component;
712

    
713
	component cmp_152 is
714
		port (
715
			eq : out std_logic;
716
			in0 : in  std_logic_vector(2 downto 0);
717
			in1 : in  std_logic_vector(2 downto 0)
718
		);
719
	end component;
720

    
721
	component cmp_154 is
722
		port (
723
			eq : out std_logic;
724
			in0 : in  std_logic_vector(2 downto 0);
725
			in1 : in  std_logic_vector(2 downto 0)
726
		);
727
	end component;
728

    
729
	component cmp_156 is
730
		port (
731
			eq : out std_logic;
732
			in0 : in  std_logic_vector(2 downto 0);
733
			in1 : in  std_logic_vector(2 downto 0)
734
		);
735
	end component;
736

    
737
	component cmp_158 is
738
		port (
739
			eq : out std_logic;
740
			in0 : in  std_logic_vector(2 downto 0);
741
			in1 : in  std_logic_vector(2 downto 0)
742
		);
743
	end component;
744

    
745
	component cmp_160 is
746
		port (
747
			eq : out std_logic;
748
			in0 : in  std_logic_vector(2 downto 0);
749
			in1 : in  std_logic_vector(2 downto 0)
750
		);
751
	end component;
752

    
753
	component cmp_127 is
754
		port (
755
			eq : out std_logic;
756
			in0 : in  std_logic_vector(2 downto 0);
757
			in1 : in  std_logic_vector(2 downto 0)
758
		);
759
	end component;
760

    
761
	component cmp_129 is
762
		port (
763
			eq : out std_logic;
764
			in0 : in  std_logic_vector(2 downto 0);
765
			in1 : in  std_logic_vector(2 downto 0)
766
		);
767
	end component;
768

    
769
	component cmp_131 is
770
		port (
771
			eq : out std_logic;
772
			in0 : in  std_logic_vector(2 downto 0);
773
			in1 : in  std_logic_vector(2 downto 0)
774
		);
775
	end component;
776

    
777
	component cmp_133 is
778
		port (
779
			eq : out std_logic;
780
			in0 : in  std_logic_vector(2 downto 0);
781
			in1 : in  std_logic_vector(2 downto 0)
782
		);
783
	end component;
784

    
785
	component cmp_135 is
786
		port (
787
			eq : out std_logic;
788
			in0 : in  std_logic_vector(2 downto 0);
789
			in1 : in  std_logic_vector(2 downto 0)
790
		);
791
	end component;
792

    
793
	-- Declaration of signals
794

    
795
	signal sig_clock : std_logic;
796
	signal sig_reset : std_logic;
797
	signal sig_222 : std_logic;
798
	signal sig_223 : std_logic;
799
	signal sig_224 : std_logic;
800
	signal sig_225 : std_logic;
801
	signal sig_226 : std_logic;
802
	signal sig_227 : std_logic;
803
	signal sig_228 : std_logic;
804
	signal sig_229 : std_logic;
805
	signal sig_230 : std_logic;
806
	signal sig_231 : std_logic;
807
	signal sig_232 : std_logic;
808
	signal sig_233 : std_logic;
809
	signal sig_234 : std_logic;
810
	signal sig_235 : std_logic;
811
	signal sig_236 : std_logic;
812
	signal sig_237 : std_logic;
813
	signal sig_238 : std_logic;
814
	signal sig_239 : std_logic;
815
	signal sig_240 : std_logic;
816
	signal sig_241 : std_logic;
817
	signal sig_242 : std_logic;
818
	signal sig_243 : std_logic;
819
	signal sig_244 : std_logic;
820
	signal sig_245 : std_logic;
821
	signal sig_246 : std_logic;
822
	signal sig_247 : std_logic;
823
	signal sig_248 : std_logic;
824
	signal sig_249 : std_logic;
825
	signal sig_250 : std_logic;
826
	signal sig_251 : std_logic;
827
	signal sig_252 : std_logic;
828
	signal sig_253 : std_logic;
829
	signal sig_254 : std_logic;
830
	signal sig_255 : std_logic;
831
	signal sig_256 : std_logic;
832
	signal sig_257 : std_logic;
833
	signal sig_258 : std_logic;
834
	signal sig_259 : std_logic;
835
	signal sig_260 : std_logic;
836
	signal sig_261 : std_logic;
837
	signal sig_262 : std_logic;
838
	signal sig_263 : std_logic;
839
	signal sig_264 : std_logic;
840
	signal sig_265 : std_logic;
841
	signal sig_266 : std_logic;
842
	signal sig_267 : std_logic;
843
	signal sig_268 : std_logic;
844
	signal sig_269 : std_logic;
845
	signal sig_270 : std_logic;
846
	signal sig_271 : std_logic;
847
	signal sig_272 : std_logic;
848
	signal sig_273 : std_logic;
849
	signal sig_274 : std_logic;
850
	signal sig_275 : std_logic;
851
	signal sig_276 : std_logic;
852
	signal sig_277 : std_logic;
853
	signal sig_278 : std_logic;
854
	signal augh_test_0 : std_logic;
855
	signal augh_test_1 : std_logic;
856
	signal sig_start : std_logic;
857
	signal test_cp_4_6 : std_logic;
858
	signal test_cp_3_7 : std_logic;
859
	signal test_cp_0_8 : std_logic;
860
	signal test_cp_1_9 : std_logic;
861
	signal test_cp_2_10 : std_logic;
862
	signal memextrct_loop_sig_13 : std_logic;
863
	signal memextrct_loop_sig_14 : std_logic;
864
	signal psc_loop_sig_12 : std_logic;
865
	signal sig_279 : std_logic_vector(15 downto 0);
866
	signal sig_280 : std_logic;
867
	signal sig_281 : std_logic;
868
	signal sig_282 : std_logic_vector(7 downto 0);
869
	signal sig_283 : std_logic;
870
	signal sig_284 : std_logic;
871
	signal sig_285 : std_logic;
872
	signal sig_286 : std_logic;
873
	signal sig_287 : std_logic;
874
	signal sig_288 : std_logic_vector(31 downto 0);
875
	signal sig_289 : std_logic_vector(31 downto 0);
876
	signal sig_290 : std_logic;
877
	signal sig_291 : std_logic;
878
	signal sig_292 : std_logic;
879
	signal sig_293 : std_logic;
880
	signal sig_294 : std_logic;
881
	signal sig_295 : std_logic_vector(8 downto 0);
882
	signal sig_296 : std_logic;
883
	signal sig_297 : std_logic_vector(3 downto 0);
884
	signal sig_298 : std_logic_vector(31 downto 0);
885
	signal sig_299 : std_logic;
886
	signal sig_300 : std_logic_vector(31 downto 0);
887
	signal sig_301 : std_logic;
888
	signal sig_302 : std_logic;
889
	signal sig_303 : std_logic;
890
	signal sig_304 : std_logic_vector(15 downto 0);
891
	signal sig_305 : std_logic;
892
	signal sig_306 : std_logic;
893
	signal sig_307 : std_logic;
894
	signal sig_308 : std_logic;
895
	signal sig_309 : std_logic;
896
	signal sig_310 : std_logic;
897
	signal sig_311 : std_logic;
898
	signal sig_312 : std_logic;
899
	signal sig_313 : std_logic;
900
	signal sig_314 : std_logic;
901
	signal sig_315 : std_logic;
902
	signal sig_316 : std_logic;
903
	signal sig_317 : std_logic;
904
	signal sig_318 : std_logic;
905
	signal sig_319 : std_logic;
906
	signal sig_320 : std_logic;
907
	signal sig_321 : std_logic;
908
	signal sig_322 : std_logic_vector(31 downto 0);
909
	signal sig_323 : std_logic_vector(7 downto 0);
910
	signal sig_324 : std_logic_vector(7 downto 0);
911
	signal sig_325 : std_logic_vector(7 downto 0);
912
	signal sig_326 : std_logic_vector(7 downto 0);
913
	signal sig_327 : std_logic_vector(7 downto 0);
914
	signal sig_328 : std_logic_vector(7 downto 0);
915
	signal sig_329 : std_logic_vector(7 downto 0);
916
	signal sig_330 : std_logic_vector(7 downto 0);
917
	signal sig_331 : std_logic_vector(7 downto 0);
918
	signal sig_332 : std_logic_vector(7 downto 0);
919
	signal sig_333 : std_logic_vector(7 downto 0);
920
	signal sig_334 : std_logic_vector(7 downto 0);
921
	signal sig_335 : std_logic_vector(7 downto 0);
922
	signal sig_336 : std_logic_vector(7 downto 0);
923
	signal sig_337 : std_logic_vector(7 downto 0);
924
	signal sig_338 : std_logic_vector(7 downto 0);
925
	signal sig_339 : std_logic_vector(31 downto 0);
926
	signal sig_340 : std_logic_vector(8 downto 0);
927
	signal sig_341 : std_logic_vector(8 downto 0);
928
	signal sig_342 : std_logic_vector(31 downto 0);
929

    
930
	-- Other inlined components
931

    
932
	signal mux_25 : std_logic;
933
	signal mux_26 : std_logic_vector(2 downto 0);
934
	signal mux_27 : std_logic;
935
	signal mux_28 : std_logic_vector(2 downto 0);
936
	signal mux_29 : std_logic;
937
	signal mux_30 : std_logic_vector(15 downto 0);
938
	signal mux_31 : std_logic;
939
	signal mux_32 : std_logic_vector(7 downto 0);
940
	signal mux_33 : std_logic;
941
	signal mux_34 : std_logic;
942
	signal mux_35 : std_logic;
943
	signal mux_36 : std_logic_vector(7 downto 0);
944
	signal mux_37 : std_logic;
945
	signal mux_38 : std_logic;
946
	signal mux_39 : std_logic;
947
	signal mux_40 : std_logic_vector(7 downto 0);
948
	signal mux_41 : std_logic;
949
	signal mux_42 : std_logic;
950
	signal mux_43 : std_logic;
951
	signal augh_main_max_iter : std_logic_vector(31 downto 0) := (others => '0');
952
	signal augh_main_std_addition : std_logic_vector(31 downto 0) := (others => '0');
953
	signal augh_main_result : std_logic_vector(31 downto 0) := (others => '0');
954
	signal augh_main_i : std_logic_vector(31 downto 0) := (others => '0');
955
	signal mux_23 : std_logic;
956
	signal mux_24 : std_logic;
957
	signal mux_44 : std_logic_vector(7 downto 0);
958
	signal mux_45 : std_logic;
959
	signal mux_46 : std_logic;
960
	signal mux_47 : std_logic;
961
	signal mux_48 : std_logic_vector(7 downto 0);
962
	signal mux_49 : std_logic;
963
	signal mux_50 : std_logic;
964
	signal mux_51 : std_logic;
965
	signal mux_52 : std_logic_vector(7 downto 0);
966
	signal mux_53 : std_logic;
967
	signal mux_54 : std_logic;
968
	signal mux_55 : std_logic;
969
	signal mux_56 : std_logic_vector(7 downto 0);
970
	signal mux_57 : std_logic;
971
	signal mux_58 : std_logic;
972
	signal mux_59 : std_logic;
973
	signal mux_60 : std_logic_vector(7 downto 0);
974
	signal mux_61 : std_logic;
975
	signal mux_62 : std_logic;
976
	signal mux_63 : std_logic;
977
	signal mux_64 : std_logic_vector(31 downto 0);
978
	signal mux_65 : std_logic;
979
	signal mux_66 : std_logic_vector(31 downto 0);
980
	signal mux_67 : std_logic;
981
	signal mux_68 : std_logic_vector(31 downto 0);
982
	signal mux_69 : std_logic;
983
	signal mux_70 : std_logic_vector(31 downto 0);
984
	signal mux_71 : std_logic;
985
	signal mux_72 : std_logic_vector(7 downto 0);
986
	signal mux_73 : std_logic;
987
	signal mux_74 : std_logic;
988
	signal mux_75 : std_logic;
989
	signal mux_76 : std_logic_vector(7 downto 0);
990
	signal mux_77 : std_logic;
991
	signal mux_78 : std_logic;
992
	signal mux_79 : std_logic;
993
	signal mux_80 : std_logic_vector(7 downto 0);
994
	signal mux_20 : std_logic;
995
	signal mux_22 : std_logic;
996
	signal and_163 : std_logic_vector(7 downto 0);
997
	signal and_164 : std_logic_vector(7 downto 0);
998
	signal and_165 : std_logic_vector(7 downto 0);
999
	signal and_166 : std_logic_vector(7 downto 0);
1000
	signal and_167 : std_logic_vector(7 downto 0);
1001
	signal and_168 : std_logic_vector(7 downto 0);
1002
	signal and_169 : std_logic_vector(7 downto 0);
1003
	signal and_182 : std_logic_vector(7 downto 0);
1004
	signal and_184 : std_logic_vector(7 downto 0);
1005
	signal and_186 : std_logic_vector(7 downto 0);
1006
	signal and_192 : std_logic;
1007
	signal and_194 : std_logic;
1008
	signal and_196 : std_logic;
1009
	signal mux_81 : std_logic;
1010
	signal mux_82 : std_logic;
1011
	signal mux_83 : std_logic;
1012
	signal mux_84 : std_logic_vector(7 downto 0);
1013
	signal mux_85 : std_logic;
1014
	signal mux_86 : std_logic;
1015
	signal mux_87 : std_logic;
1016
	signal mux_88 : std_logic_vector(7 downto 0);
1017
	signal mux_89 : std_logic;
1018
	signal mux_90 : std_logic;
1019
	signal mux_91 : std_logic;
1020
	signal mux_92 : std_logic_vector(7 downto 0);
1021
	signal mux_93 : std_logic;
1022
	signal mux_94 : std_logic;
1023
	signal mux_95 : std_logic;
1024
	signal mux_96 : std_logic_vector(7 downto 0);
1025
	signal mux_97 : std_logic;
1026
	signal mux_98 : std_logic;
1027
	signal mux_99 : std_logic;
1028
	signal mux_100 : std_logic_vector(7 downto 0);
1029
	signal mux_101 : std_logic;
1030
	signal mux_102 : std_logic;
1031
	signal mux_103 : std_logic;
1032
	signal mux_106 : std_logic;
1033
	signal mux_108 : std_logic;
1034
	signal mux_109 : std_logic_vector(63 downto 0);
1035
	signal mux_110 : std_logic;
1036
	signal and_116 : std_logic;
1037
	signal not_122 : std_logic;
1038
	signal or_143 : std_logic_vector(7 downto 0);
1039
	signal and_147 : std_logic_vector(7 downto 0);
1040
	signal and_149 : std_logic_vector(7 downto 0);
1041
	signal and_151 : std_logic_vector(7 downto 0);
1042
	signal and_153 : std_logic_vector(7 downto 0);
1043
	signal and_155 : std_logic_vector(7 downto 0);
1044
	signal and_157 : std_logic_vector(7 downto 0);
1045
	signal and_159 : std_logic_vector(7 downto 0);
1046
	signal or_161 : std_logic_vector(7 downto 0);
1047
	signal and_162 : std_logic_vector(7 downto 0);
1048
	signal or_172 : std_logic_vector(7 downto 0);
1049
	signal and_173 : std_logic_vector(7 downto 0);
1050
	signal and_175 : std_logic_vector(7 downto 0);
1051
	signal and_177 : std_logic_vector(7 downto 0);
1052
	signal and_179 : std_logic_vector(7 downto 0);
1053
	signal and_181 : std_logic_vector(7 downto 0);
1054
	signal and_190 : std_logic;
1055
	signal and_197 : std_logic;
1056
	signal and_199 : std_logic;
1057
	signal and_201 : std_logic;
1058
	signal and_203 : std_logic;
1059
	signal or_205 : std_logic_vector(7 downto 0);
1060
	signal and_206 : std_logic_vector(7 downto 0);
1061
	signal and_207 : std_logic_vector(7 downto 0);
1062
	signal and_208 : std_logic_vector(7 downto 0);
1063
	signal and_209 : std_logic_vector(7 downto 0);
1064
	signal and_210 : std_logic_vector(7 downto 0);
1065
	signal and_211 : std_logic_vector(7 downto 0);
1066
	signal and_212 : std_logic_vector(7 downto 0);
1067
	signal and_213 : std_logic_vector(7 downto 0);
1068
	signal psc_loop_reg_3 : std_logic_vector(15 downto 0) := (others => '0');
1069
	signal cp_id_reg_4 : std_logic_vector(2 downto 0) := (others => '0');
1070
	signal cp_id_reg_stable_5 : std_logic_vector(2 downto 0) := (others => '0');
1071
	signal psc_stuff_reg_11 : std_logic_vector(60 downto 0) := "0000000000000000000000000000000000000000000000000000000000000";
1072
	signal and_144 : std_logic_vector(7 downto 0);
1073

    
1074
	-- This utility function is used for to generate concatenations of std_logic
1075

    
1076
	-- Little utility function to ease concatenation of an std_logic
1077
	-- and explicitely return an std_logic_vector
1078
	function repeat(N: natural; B: std_logic) return std_logic_vector is
1079
		variable result: std_logic_vector(N-1 downto 0);
1080
	begin
1081
		result := (others => B);
1082
		return result;
1083
	end;
1084

    
1085
begin
1086

    
1087
	-- Instantiation of components
1088

    
1089
	v_split0_i : v_split0 port map (
1090
		clk => sig_clock,
1091
		ra0_data => sig_338,
1092
		wa0_data => mux_100,
1093
		wa0_addr => mux_101,
1094
		wa0_en => mux_102,
1095
		ra0_addr => mux_103
1096
	);
1097

    
1098
	v_split1_i : v_split1 port map (
1099
		clk => sig_clock,
1100
		ra0_data => sig_337,
1101
		wa0_data => mux_96,
1102
		wa0_addr => mux_97,
1103
		wa0_en => mux_98,
1104
		ra0_addr => mux_99
1105
	);
1106

    
1107
	v_split2_i : v_split2 port map (
1108
		clk => sig_clock,
1109
		ra0_data => sig_336,
1110
		wa0_data => mux_92,
1111
		wa0_addr => mux_93,
1112
		wa0_en => mux_94,
1113
		ra0_addr => mux_95
1114
	);
1115

    
1116
	v_split3_i : v_split3 port map (
1117
		clk => sig_clock,
1118
		ra0_data => sig_335,
1119
		wa0_data => mux_88,
1120
		wa0_addr => mux_89,
1121
		wa0_en => mux_90,
1122
		ra0_addr => mux_91
1123
	);
1124

    
1125
	v_split4_i : v_split4 port map (
1126
		clk => sig_clock,
1127
		ra0_data => sig_334,
1128
		wa0_data => mux_84,
1129
		wa0_addr => mux_85,
1130
		wa0_en => mux_86,
1131
		ra0_addr => mux_87
1132
	);
1133

    
1134
	v_split5_i : v_split5 port map (
1135
		clk => sig_clock,
1136
		ra0_data => sig_333,
1137
		wa0_data => mux_80,
1138
		wa0_addr => mux_81,
1139
		wa0_en => mux_82,
1140
		ra0_addr => mux_83
1141
	);
1142

    
1143
	v_split6_i : v_split6 port map (
1144
		clk => sig_clock,
1145
		ra0_data => sig_332,
1146
		wa0_data => mux_76,
1147
		wa0_addr => mux_77,
1148
		wa0_en => mux_78,
1149
		ra0_addr => mux_79
1150
	);
1151

    
1152
	v_split7_i : v_split7 port map (
1153
		clk => sig_clock,
1154
		ra0_data => sig_331,
1155
		wa0_data => mux_72,
1156
		wa0_addr => mux_73,
1157
		wa0_en => mux_74,
1158
		ra0_addr => mux_75
1159
	);
1160

    
1161
	w_split0_i : w_split0 port map (
1162
		clk => sig_clock,
1163
		ra0_data => sig_330,
1164
		wa0_data => mux_60,
1165
		wa0_addr => mux_61,
1166
		wa0_en => mux_62,
1167
		ra0_addr => mux_63
1168
	);
1169

    
1170
	w_split1_i : w_split1 port map (
1171
		clk => sig_clock,
1172
		ra0_data => sig_329,
1173
		wa0_data => mux_56,
1174
		wa0_addr => mux_57,
1175
		wa0_en => mux_58,
1176
		ra0_addr => mux_59
1177
	);
1178

    
1179
	w_split2_i : w_split2 port map (
1180
		clk => sig_clock,
1181
		ra0_data => sig_328,
1182
		wa0_data => mux_52,
1183
		wa0_addr => mux_53,
1184
		wa0_en => mux_54,
1185
		ra0_addr => mux_55
1186
	);
1187

    
1188
	w_split3_i : w_split3 port map (
1189
		clk => sig_clock,
1190
		ra0_data => sig_327,
1191
		wa0_data => mux_48,
1192
		wa0_addr => mux_49,
1193
		wa0_en => mux_50,
1194
		ra0_addr => mux_51
1195
	);
1196

    
1197
	w_split4_i : w_split4 port map (
1198
		clk => sig_clock,
1199
		ra0_data => sig_326,
1200
		wa0_data => mux_44,
1201
		wa0_addr => mux_45,
1202
		wa0_en => mux_46,
1203
		ra0_addr => mux_47
1204
	);
1205

    
1206
	w_split5_i : w_split5 port map (
1207
		clk => sig_clock,
1208
		ra0_data => sig_325,
1209
		wa0_data => mux_40,
1210
		wa0_addr => mux_41,
1211
		wa0_en => mux_42,
1212
		ra0_addr => mux_43
1213
	);
1214

    
1215
	w_split6_i : w_split6 port map (
1216
		clk => sig_clock,
1217
		ra0_data => sig_324,
1218
		wa0_data => mux_36,
1219
		wa0_addr => mux_37,
1220
		wa0_en => mux_38,
1221
		ra0_addr => mux_39
1222
	);
1223

    
1224
	w_split7_i : w_split7 port map (
1225
		clk => sig_clock,
1226
		ra0_data => sig_323,
1227
		wa0_data => mux_32,
1228
		wa0_addr => mux_33,
1229
		wa0_en => mux_34,
1230
		ra0_addr => mux_35
1231
	);
1232

    
1233
	add_171_i : add_171 port map (
1234
		result => sig_322,
1235
		in_a => sig_342,
1236
		in_b => augh_main_std_addition
1237
	);
1238

    
1239
	cmp_183_i : cmp_183 port map (
1240
		eq => sig_321,
1241
		in0 => "010",
1242
		in1 => augh_main_i(2 downto 0)
1243
	);
1244

    
1245
	cmp_185_i : cmp_185 port map (
1246
		eq => sig_320,
1247
		in0 => "001",
1248
		in1 => augh_main_i(2 downto 0)
1249
	);
1250

    
1251
	cmp_193_i : cmp_193 port map (
1252
		eq => sig_319,
1253
		in0 => "110",
1254
		in1 => augh_main_i(2 downto 0)
1255
	);
1256

    
1257
	cmp_195_i : cmp_195 port map (
1258
		eq => sig_318,
1259
		in0 => "101",
1260
		in1 => augh_main_i(2 downto 0)
1261
	);
1262

    
1263
	muxb_120_i : muxb_120 port map (
1264
		in_sel => cp_en,
1265
		out_data => sig_317,
1266
		in_data0 => '0',
1267
		in_data1 => '1'
1268
	);
1269

    
1270
	muxb_124_i : muxb_124 port map (
1271
		in_sel => not_122,
1272
		out_data => sig_316,
1273
		in_data0 => '0',
1274
		in_data1 => '1'
1275
	);
1276

    
1277
	cmp_128_i : cmp_128 port map (
1278
		eq => sig_315,
1279
		in0 => "101",
1280
		in1 => augh_main_i(2 downto 0)
1281
	);
1282

    
1283
	cmp_130_i : cmp_130 port map (
1284
		eq => sig_314,
1285
		in0 => "011",
1286
		in1 => augh_main_i(2 downto 0)
1287
	);
1288

    
1289
	cmp_132_i : cmp_132 port map (
1290
		eq => sig_313,
1291
		in0 => "001",
1292
		in1 => augh_main_i(2 downto 0)
1293
	);
1294

    
1295
	cmp_136_i : cmp_136 port map (
1296
		eq => sig_312,
1297
		in0 => "110",
1298
		in1 => sig_298(2 downto 0)
1299
	);
1300

    
1301
	cmp_137_i : cmp_137 port map (
1302
		eq => sig_311,
1303
		in0 => "101",
1304
		in1 => sig_298(2 downto 0)
1305
	);
1306

    
1307
	cmp_138_i : cmp_138 port map (
1308
		eq => sig_310,
1309
		in0 => "100",
1310
		in1 => sig_298(2 downto 0)
1311
	);
1312

    
1313
	cmp_139_i : cmp_139 port map (
1314
		eq => sig_309,
1315
		in0 => "011",
1316
		in1 => sig_298(2 downto 0)
1317
	);
1318

    
1319
	cmp_140_i : cmp_140 port map (
1320
		eq => sig_308,
1321
		in0 => "010",
1322
		in1 => sig_298(2 downto 0)
1323
	);
1324

    
1325
	cmp_141_i : cmp_141 port map (
1326
		eq => sig_307,
1327
		in0 => "001",
1328
		in1 => sig_298(2 downto 0)
1329
	);
1330

    
1331
	cmp_142_i : cmp_142 port map (
1332
		eq => sig_306,
1333
		in0 => "000",
1334
		in1 => sig_298(2 downto 0)
1335
	);
1336

    
1337
	muxb_117_i : muxb_117 port map (
1338
		in_sel => cp_en,
1339
		out_data => sig_305,
1340
		in_data0 => '0',
1341
		in_data1 => '1'
1342
	);
1343

    
1344
	add_118_i : add_118 port map (
1345
		result => sig_304,
1346
		in_a => psc_loop_reg_3,
1347
		in_b => "0000000000000001"
1348
	);
1349

    
1350
	cmp_119_i : cmp_119 port map (
1351
		ne => sig_303,
1352
		in0 => "0000000000000001",
1353
		in1 => psc_loop_reg_3
1354
	);
1355

    
1356
	muxb_121_i : muxb_121 port map (
1357
		in_sel => not_122,
1358
		out_data => sig_302,
1359
		in_data0 => '0',
1360
		in_data1 => '1'
1361
	);
1362

    
1363
	muxb_123_i : muxb_123 port map (
1364
		in_sel => not_122,
1365
		out_data => sig_301,
1366
		in_data0 => '0',
1367
		in_data1 => '1'
1368
	);
1369

    
1370
	sub_125_i : sub_125 port map (
1371
		le => augh_test_1,
1372
		sign => '1',
1373
		result => sig_300,
1374
		in_a => augh_main_i,
1375
		in_b => "00000000000000000000000000000111"
1376
	);
1377

    
1378
	cmp_126_i : cmp_126 port map (
1379
		eq => sig_299,
1380
		in0 => "111",
1381
		in1 => augh_main_i(2 downto 0)
1382
	);
1383

    
1384
	add_134_i : add_134 port map (
1385
		result => sig_298,
1386
		in_a => augh_main_i,
1387
		in_b => "00000000000000000000000000000001"
1388
	);
1389

    
1390
	sub_145_i : sub_145 port map (
1391
		result => sig_297,
1392
		in_a => augh_main_max_iter(3 downto 0),
1393
		in_b => "0001"
1394
	);
1395

    
1396
	cmp_146_i : cmp_146 port map (
1397
		eq => sig_296,
1398
		in0 => "111",
1399
		in1 => sig_297(2 downto 0)
1400
	);
1401

    
1402
	add_170_i : add_170 port map (
1403
		result => sig_295,
1404
		in_a => sig_341,
1405
		in_b => sig_340
1406
	);
1407

    
1408
	cmp_174_i : cmp_174 port map (
1409
		eq => sig_294,
1410
		in0 => "111",
1411
		in1 => augh_main_i(2 downto 0)
1412
	);
1413

    
1414
	cmp_176_i : cmp_176 port map (
1415
		eq => sig_293,
1416
		in0 => "110",
1417
		in1 => augh_main_i(2 downto 0)
1418
	);
1419

    
1420
	cmp_178_i : cmp_178 port map (
1421
		eq => sig_292,
1422
		in0 => "101",
1423
		in1 => augh_main_i(2 downto 0)
1424
	);
1425

    
1426
	cmp_180_i : cmp_180 port map (
1427
		eq => sig_291,
1428
		in0 => "100",
1429
		in1 => augh_main_i(2 downto 0)
1430
	);
1431

    
1432
	cmp_187_i : cmp_187 port map (
1433
		eq => sig_290,
1434
		in0 => "000",
1435
		in1 => augh_main_i(2 downto 0)
1436
	);
1437

    
1438
	add_188_i : add_188 port map (
1439
		result => sig_289,
1440
		in_a => augh_main_result,
1441
		in_b => sig_339
1442
	);
1443

    
1444
	sub_189_i : sub_189 port map (
1445
		lt => augh_test_0,
1446
		sign => '1',
1447
		result => sig_288,
1448
		in_a => augh_main_i,
1449
		in_b => augh_main_max_iter
1450
	);
1451

    
1452
	cmp_191_i : cmp_191 port map (
1453
		eq => sig_287,
1454
		in0 => "111",
1455
		in1 => augh_main_i(2 downto 0)
1456
	);
1457

    
1458
	cmp_198_i : cmp_198 port map (
1459
		eq => sig_286,
1460
		in0 => "011",
1461
		in1 => augh_main_i(2 downto 0)
1462
	);
1463

    
1464
	cmp_200_i : cmp_200 port map (
1465
		eq => sig_285,
1466
		in0 => "010",
1467
		in1 => augh_main_i(2 downto 0)
1468
	);
1469

    
1470
	cmp_202_i : cmp_202 port map (
1471
		eq => sig_284,
1472
		in0 => "001",
1473
		in1 => augh_main_i(2 downto 0)
1474
	);
1475

    
1476
	cmp_204_i : cmp_204 port map (
1477
		eq => sig_283,
1478
		in0 => "000",
1479
		in1 => augh_main_i(2 downto 0)
1480
	);
1481

    
1482
	add_214_i : add_214 port map (
1483
		result => sig_282,
1484
		in_a => or_205,
1485
		in_b => augh_main_i(7 downto 0)
1486
	);
1487

    
1488
	cmp_215_i : cmp_215 port map (
1489
		eq => sig_281,
1490
		in0 => "001",
1491
		in1 => cp_id_reg_stable_5
1492
	);
1493

    
1494
	muxb_219_i : muxb_219 port map (
1495
		in_sel => cp_en,
1496
		out_data => sig_280,
1497
		in_data0 => '0',
1498
		in_data1 => '1'
1499
	);
1500

    
1501
	add_220_i : add_220 port map (
1502
		result => sig_279,
1503
		in_a => psc_loop_reg_3,
1504
		in_b => "0000000000000001"
1505
	);
1506

    
1507
	cmp_221_i : cmp_221 port map (
1508
		ne => psc_loop_sig_12,
1509
		in0 => "0000000000000010",
1510
		in1 => psc_loop_reg_3
1511
	);
1512

    
1513
	cmp_111_i : cmp_111 port map (
1514
		eq => test_cp_2_10,
1515
		in0 => "010",
1516
		in1 => cp_id_reg_stable_5
1517
	);
1518

    
1519
	cmp_113_i : cmp_113 port map (
1520
		eq => sig_278,
1521
		in0 => "000",
1522
		in1 => cp_id_reg_stable_5
1523
	);
1524

    
1525
	cmp_216_i : cmp_216 port map (
1526
		eq => sig_277,
1527
		in0 => "000",
1528
		in1 => cp_id_reg_stable_5
1529
	);
1530

    
1531
	cmp_217_i : cmp_217 port map (
1532
		eq => sig_276,
1533
		in0 => "011",
1534
		in1 => cp_id_reg_stable_5
1535
	);
1536

    
1537
	cmp_218_i : cmp_218 port map (
1538
		eq => sig_275,
1539
		in0 => "100",
1540
		in1 => cp_id_reg_stable_5
1541
	);
1542

    
1543
	fsm_15_i : fsm_15 port map (
1544
		clock => sig_clock,
1545
		reset => sig_reset,
1546
		out3 => sig_274,
1547
		out157 => sig_273,
1548
		out159 => sig_272,
1549
		out160 => sig_271,
1550
		out171 => sig_270,
1551
		out172 => sig_269,
1552
		out173 => sig_268,
1553
		out175 => sig_267,
1554
		out178 => sig_266,
1555
		in0 => test_cp_4_6,
1556
		out0 => sig_265,
1557
		in5 => memextrct_loop_sig_14,
1558
		in6 => memextrct_loop_sig_13,
1559
		in7 => stdout_ack,
1560
		out35 => sig_264,
1561
		out39 => sig_263,
1562
		out40 => sig_262,
1563
		out41 => sig_261,
1564
		out44 => sig_260,
1565
		out46 => sig_259,
1566
		out140 => sig_258,
1567
		in8 => cp_en,
1568
		in9 => stdin_ack,
1569
		in10 => augh_test_1,
1570
		in11 => augh_test_0,
1571
		in12 => cp_rest,
1572
		in13 => sig_start,
1573
		in14 => psc_loop_sig_12,
1574
		out65 => sig_257,
1575
		in1 => test_cp_3_7,
1576
		in2 => test_cp_0_8,
1577
		in3 => test_cp_1_9,
1578
		in4 => test_cp_2_10,
1579
		out225 => sig_256,
1580
		out227 => sig_255,
1581
		out231 => sig_254,
1582
		out235 => sig_253,
1583
		out236 => sig_252,
1584
		out237 => sig_251,
1585
		out238 => sig_250,
1586
		out97 => sig_249,
1587
		out98 => sig_248,
1588
		out101 => sig_247,
1589
		out102 => sig_246,
1590
		out124 => sig_245,
1591
		out125 => sig_244,
1592
		out80 => sig_243,
1593
		out81 => sig_242,
1594
		out84 => sig_241,
1595
		out86 => sig_240,
1596
		out88 => sig_239,
1597
		out93 => sig_238,
1598
		out94 => sig_237
1599
	);
1600

    
1601
	cmp_112_i : cmp_112 port map (
1602
		eq => sig_236,
1603
		in0 => "001",
1604
		in1 => cp_id_reg_stable_5
1605
	);
1606

    
1607
	cmp_114_i : cmp_114 port map (
1608
		eq => sig_235,
1609
		in0 => "011",
1610
		in1 => cp_id_reg_stable_5
1611
	);
1612

    
1613
	cmp_115_i : cmp_115 port map (
1614
		eq => sig_234,
1615
		in0 => "100",
1616
		in1 => cp_id_reg_stable_5
1617
	);
1618

    
1619
	cmp_148_i : cmp_148 port map (
1620
		eq => sig_233,
1621
		in0 => "110",
1622
		in1 => sig_297(2 downto 0)
1623
	);
1624

    
1625
	cmp_150_i : cmp_150 port map (
1626
		eq => sig_232,
1627
		in0 => "101",
1628
		in1 => sig_297(2 downto 0)
1629
	);
1630

    
1631
	cmp_152_i : cmp_152 port map (
1632
		eq => sig_231,
1633
		in0 => "100",
1634
		in1 => sig_297(2 downto 0)
1635
	);
1636

    
1637
	cmp_154_i : cmp_154 port map (
1638
		eq => sig_230,
1639
		in0 => "011",
1640
		in1 => sig_297(2 downto 0)
1641
	);
1642

    
1643
	cmp_156_i : cmp_156 port map (
1644
		eq => sig_229,
1645
		in0 => "010",
1646
		in1 => sig_297(2 downto 0)
1647
	);
1648

    
1649
	cmp_158_i : cmp_158 port map (
1650
		eq => sig_228,
1651
		in0 => "001",
1652
		in1 => sig_297(2 downto 0)
1653
	);
1654

    
1655
	cmp_160_i : cmp_160 port map (
1656
		eq => sig_227,
1657
		in0 => "000",
1658
		in1 => sig_297(2 downto 0)
1659
	);
1660

    
1661
	cmp_127_i : cmp_127 port map (
1662
		eq => sig_226,
1663
		in0 => "110",
1664
		in1 => augh_main_i(2 downto 0)
1665
	);
1666

    
1667
	cmp_129_i : cmp_129 port map (
1668
		eq => sig_225,
1669
		in0 => "100",
1670
		in1 => augh_main_i(2 downto 0)
1671
	);
1672

    
1673
	cmp_131_i : cmp_131 port map (
1674
		eq => sig_224,
1675
		in0 => "010",
1676
		in1 => augh_main_i(2 downto 0)
1677
	);
1678

    
1679
	cmp_133_i : cmp_133 port map (
1680
		eq => sig_223,
1681
		in0 => "000",
1682
		in1 => augh_main_i(2 downto 0)
1683
	);
1684

    
1685
	cmp_135_i : cmp_135 port map (
1686
		eq => sig_222,
1687
		in0 => "111",
1688
		in1 => sig_298(2 downto 0)
1689
	);
1690

    
1691
	-- Behaviour of component 'mux_25' model 'mux'
1692
	mux_25 <=
1693
		(sig_274 and sig_234) or
1694
		(sig_254 and sig_275);
1695

    
1696
	-- Behaviour of component 'mux_26' model 'mux'
1697
	mux_26 <=
1698
		(repeat(3, sig_243) and "010") or
1699
		(repeat(3, sig_253) and cp_din(2 downto 0)) or
1700
		(repeat(3, sig_240) and "001") or
1701
		(repeat(3, sig_271) and "011") or
1702
		(repeat(3, sig_267) and "100");
1703

    
1704
	-- Behaviour of component 'mux_27' model 'mux'
1705
	mux_27 <=
1706
		(sig_242 and '1') or
1707
		(sig_252 and cp_rest);
1708

    
1709
	-- Behaviour of component 'mux_28' model 'mux'
1710
	mux_28 <=
1711
		(repeat(3, sig_243) and "010") or
1712
		(repeat(3, sig_251) and augh_main_result(2 downto 0)) or
1713
		(repeat(3, sig_240) and "001") or
1714
		(repeat(3, sig_271) and "011") or
1715
		(repeat(3, sig_267) and "100");
1716

    
1717
	-- Behaviour of component 'mux_29' model 'mux'
1718
	mux_29 <=
1719
		(sig_242 and '1') or
1720
		(sig_250 and cp_en);
1721

    
1722
	-- Behaviour of component 'mux_30' model 'mux'
1723
	mux_30 <=
1724
		(repeat(16, sig_262) and sig_304) or
1725
		(repeat(16, sig_251) and sig_279);
1726

    
1727
	-- Behaviour of component 'mux_31' model 'mux'
1728
	mux_31 <=
1729
		(sig_261 and cp_en) or
1730
		(sig_260 and '1');
1731

    
1732
	-- Behaviour of component 'mux_32' model 'mux'
1733
	mux_32 <=
1734
		(repeat(8, sig_263) and cp_din(7 downto 0)) or
1735
		(repeat(8, sig_267) and sig_282);
1736

    
1737
	-- Behaviour of component 'mux_33' model 'mux'
1738
	mux_33 <=
1739
		(sig_263 and psc_loop_reg_3(0)) or
1740
		(sig_267 and augh_main_i(3));
1741

    
1742
	-- Behaviour of component 'mux_34' model 'mux'
1743
	mux_34 <=
1744
		(sig_264 and and_116) or
1745
		(sig_266 and and_190);
1746

    
1747
	-- Behaviour of component 'mux_35' model 'mux'
1748
	mux_35 <=
1749
		(sig_263 and psc_loop_reg_3(0)) or
1750
		(sig_258 and sig_297(3)) or
1751
		(sig_267 and augh_main_i(3));
1752

    
1753
	-- Behaviour of component 'mux_36' model 'mux'
1754
	mux_36 <=
1755
		(repeat(8, sig_263) and cp_din(15 downto 8)) or
1756
		(repeat(8, sig_267) and sig_282);
1757

    
1758
	-- Behaviour of component 'mux_37' model 'mux'
1759
	mux_37 <=
1760
		(sig_263 and psc_loop_reg_3(0)) or
1761
		(sig_267 and augh_main_i(3));
1762

    
1763
	-- Behaviour of component 'mux_38' model 'mux'
1764
	mux_38 <=
1765
		(sig_264 and and_116) or
1766
		(sig_266 and and_192);
1767

    
1768
	-- Behaviour of component 'mux_39' model 'mux'
1769
	mux_39 <=
1770
		(sig_263 and psc_loop_reg_3(0)) or
1771
		(sig_258 and sig_297(3)) or
1772
		(sig_267 and augh_main_i(3));
1773

    
1774
	-- Behaviour of component 'mux_40' model 'mux'
1775
	mux_40 <=
1776
		(repeat(8, sig_263) and cp_din(23 downto 16)) or
1777
		(repeat(8, sig_267) and sig_282);
1778

    
1779
	-- Behaviour of component 'mux_41' model 'mux'
1780
	mux_41 <=
1781
		(sig_263 and psc_loop_reg_3(0)) or
1782
		(sig_267 and augh_main_i(3));
1783

    
1784
	-- Behaviour of component 'mux_42' model 'mux'
1785
	mux_42 <=
1786
		(sig_264 and and_116) or
1787
		(sig_266 and and_194);
1788

    
1789
	-- Behaviour of component 'mux_43' model 'mux'
1790
	mux_43 <=
1791
		(sig_263 and psc_loop_reg_3(0)) or
1792
		(sig_258 and sig_297(3)) or
1793
		(sig_267 and augh_main_i(3));
1794

    
1795
	-- Behaviour of component 'mux_23' model 'mux'
1796
	mux_23 <=
1797
		(sig_274 and sig_278) or
1798
		(sig_254 and sig_277);
1799

    
1800
	-- Behaviour of component 'mux_24' model 'mux'
1801
	mux_24 <=
1802
		(sig_274 and sig_235) or
1803
		(sig_254 and sig_276);
1804

    
1805
	-- Behaviour of component 'mux_44' model 'mux'
1806
	mux_44 <=
1807
		(repeat(8, sig_263) and cp_din(31 downto 24)) or
1808
		(repeat(8, sig_267) and sig_282);
1809

    
1810
	-- Behaviour of component 'mux_45' model 'mux'
1811
	mux_45 <=
1812
		(sig_263 and psc_loop_reg_3(0)) or
1813
		(sig_249 and '1') or
1814
		(sig_267 and augh_main_i(3));
1815

    
1816
	-- Behaviour of component 'mux_46' model 'mux'
1817
	mux_46 <=
1818
		(sig_264 and and_116) or
1819
		(sig_248 and '1') or
1820
		(sig_266 and and_196);
1821

    
1822
	-- Behaviour of component 'mux_47' model 'mux'
1823
	mux_47 <=
1824
		(sig_263 and psc_loop_reg_3(0)) or
1825
		(sig_258 and sig_297(3)) or
1826
		(sig_267 and augh_main_i(3));
1827

    
1828
	-- Behaviour of component 'mux_48' model 'mux'
1829
	mux_48 <=
1830
		(repeat(8, sig_263) and cp_din(39 downto 32)) or
1831
		(repeat(8, sig_267) and sig_282);
1832

    
1833
	-- Behaviour of component 'mux_49' model 'mux'
1834
	mux_49 <=
1835
		(sig_263 and psc_loop_reg_3(0)) or
1836
		(sig_267 and augh_main_i(3));
1837

    
1838
	-- Behaviour of component 'mux_50' model 'mux'
1839
	mux_50 <=
1840
		(sig_264 and and_116) or
1841
		(sig_266 and and_197);
1842

    
1843
	-- Behaviour of component 'mux_51' model 'mux'
1844
	mux_51 <=
1845
		(sig_263 and psc_loop_reg_3(0)) or
1846
		(sig_258 and sig_297(3)) or
1847
		(sig_267 and augh_main_i(3));
1848

    
1849
	-- Behaviour of component 'mux_52' model 'mux'
1850
	mux_52 <=
1851
		(repeat(8, sig_263) and cp_din(47 downto 40)) or
1852
		(repeat(8, sig_267) and sig_282);
1853

    
1854
	-- Behaviour of component 'mux_53' model 'mux'
1855
	mux_53 <=
1856
		(sig_263 and psc_loop_reg_3(0)) or
1857
		(sig_267 and augh_main_i(3));
1858

    
1859
	-- Behaviour of component 'mux_54' model 'mux'
1860
	mux_54 <=
1861
		(sig_264 and and_116) or
1862
		(sig_266 and and_199);
1863

    
1864
	-- Behaviour of component 'mux_55' model 'mux'
1865
	mux_55 <=
1866
		(sig_263 and psc_loop_reg_3(0)) or
1867
		(sig_258 and sig_297(3)) or
1868
		(sig_267 and augh_main_i(3));
1869

    
1870
	-- Behaviour of component 'mux_56' model 'mux'
1871
	mux_56 <=
1872
		(repeat(8, sig_263) and cp_din(55 downto 48)) or
1873
		(repeat(8, sig_267) and sig_282) or
1874
		(repeat(8, sig_256) and "00000011");
1875

    
1876
	-- Behaviour of component 'mux_57' model 'mux'
1877
	mux_57 <=
1878
		(sig_263 and psc_loop_reg_3(0)) or
1879
		(sig_267 and augh_main_i(3));
1880

    
1881
	-- Behaviour of component 'mux_58' model 'mux'
1882
	mux_58 <=
1883
		(sig_264 and and_116) or
1884
		(sig_266 and and_201) or
1885
		(sig_255 and '1');
1886

    
1887
	-- Behaviour of component 'mux_59' model 'mux'
1888
	mux_59 <=
1889
		(sig_263 and psc_loop_reg_3(0)) or
1890
		(sig_258 and sig_297(3)) or
1891
		(sig_267 and augh_main_i(3));
1892

    
1893
	-- Behaviour of component 'mux_60' model 'mux'
1894
	mux_60 <=
1895
		(repeat(8, sig_263) and cp_din(63 downto 56)) or
1896
		(repeat(8, sig_267) and sig_282);
1897

    
1898
	-- Behaviour of component 'mux_61' model 'mux'
1899
	mux_61 <=
1900
		(sig_263 and psc_loop_reg_3(0)) or
1901
		(sig_267 and augh_main_i(3));
1902

    
1903
	-- Behaviour of component 'mux_62' model 'mux'
1904
	mux_62 <=
1905
		(sig_264 and and_116) or
1906
		(sig_266 and and_203);
1907

    
1908
	-- Behaviour of component 'mux_63' model 'mux'
1909
	mux_63 <=
1910
		(sig_263 and psc_loop_reg_3(0)) or
1911
		(sig_258 and sig_297(3)) or
1912
		(sig_267 and augh_main_i(3));
1913

    
1914
	-- Behaviour of component 'mux_64' model 'mux'
1915
	mux_64 <=
1916
		(repeat(32, sig_269) and sig_298) or
1917
		(repeat(32, sig_251) and augh_main_std_addition);
1918

    
1919
	-- Behaviour of component 'mux_65' model 'mux'
1920
	mux_65 <=
1921
		(sig_272 and '1') or
1922
		(sig_268 and not_122) or
1923
		(sig_250 and cp_en);
1924

    
1925
	-- Behaviour of component 'mux_66' model 'mux'
1926
	mux_66 <=
1927
		(repeat(32, sig_258) and sig_322) or
1928
		(repeat(32, sig_271) and sig_289) or
1929
		(repeat(32, sig_251) and augh_main_max_iter);
1930

    
1931
	-- Behaviour of component 'mux_67' model 'mux'
1932
	mux_67 <=
1933
		(sig_273 and '1') or
1934
		(sig_270 and not_122) or
1935
		(sig_250 and cp_en);
1936

    
1937
	-- Behaviour of component 'mux_68' model 'mux'
1938
	mux_68 <=
1939
		(repeat(32, sig_237) and stdin_data) or
1940
		(repeat(32, sig_251) and cp_din(63 downto 32));
1941

    
1942
	-- Behaviour of component 'mux_69' model 'mux'
1943
	mux_69 <=
1944
		(sig_238 and not_122) or
1945
		(sig_250 and cp_en);
1946

    
1947
	-- Behaviour of component 'mux_70' model 'mux'
1948
	mux_70 <=
1949
		(repeat(32, sig_240) and stdin_data) or
1950
		(repeat(32, sig_251) and cp_din(31 downto 0));
1951

    
1952
	-- Behaviour of component 'mux_71' model 'mux'
1953
	mux_71 <=
1954
		(sig_239 and not_122) or
1955
		(sig_250 and cp_en);
1956

    
1957
	-- Behaviour of component 'mux_72' model 'mux'
1958
	mux_72 <=
1959
		(repeat(8, sig_259) and cp_din(7 downto 0)) or
1960
		(repeat(8, sig_267) and augh_main_i(7 downto 0));
1961

    
1962
	-- Behaviour of component 'mux_73' model 'mux'
1963
	mux_73 <=
1964
		(sig_259 and psc_loop_reg_3(0)) or
1965
		(sig_247 and augh_main_i(3)) or
1966
		(sig_245 and sig_298(3));
1967

    
1968
	-- Behaviour of component 'mux_74' model 'mux'
1969
	mux_74 <=
1970
		(sig_257 and and_116) or
1971
		(sig_246 and sig_299) or
1972
		(sig_244 and sig_222) or
1973
		(sig_266 and and_190);
1974

    
1975
	-- Behaviour of component 'mux_75' model 'mux'
1976
	mux_75 <=
1977
		(sig_259 and psc_loop_reg_3(0)) or
1978
		(sig_258 and sig_297(3)) or
1979
		(sig_271 and augh_main_i(3));
1980

    
1981
	-- Behaviour of component 'mux_76' model 'mux'
1982
	mux_76 <=
1983
		(repeat(8, sig_259) and cp_din(15 downto 8)) or
1984
		(repeat(8, sig_267) and augh_main_i(7 downto 0));
1985

    
1986
	-- Behaviour of component 'mux_77' model 'mux'
1987
	mux_77 <=
1988
		(sig_259 and psc_loop_reg_3(0)) or
1989
		(sig_247 and augh_main_i(3)) or
1990
		(sig_245 and sig_298(3));
1991

    
1992
	-- Behaviour of component 'mux_78' model 'mux'
1993
	mux_78 <=
1994
		(sig_257 and and_116) or
1995
		(sig_246 and sig_226) or
1996
		(sig_244 and sig_312) or
1997
		(sig_266 and and_192);
1998

    
1999
	-- Behaviour of component 'mux_79' model 'mux'
2000
	mux_79 <=
2001
		(sig_259 and psc_loop_reg_3(0)) or
2002
		(sig_258 and sig_297(3)) or
2003
		(sig_271 and augh_main_i(3));
2004

    
2005
	-- Behaviour of component 'mux_80' model 'mux'
2006
	mux_80 <=
2007
		(repeat(8, sig_259) and cp_din(23 downto 16)) or
2008
		(repeat(8, sig_267) and augh_main_i(7 downto 0)) or
2009
		(repeat(8, sig_256) and "00001100");
2010

    
2011
	-- Behaviour of component 'mux_20' model 'mux'
2012
	mux_20 <=
2013
		(sig_250 and cp_en);
2014

    
2015
	-- Behaviour of component 'mux_22' model 'mux'
2016
	mux_22 <=
2017
		(sig_274 and sig_236) or
2018
		(sig_254 and sig_281);
2019

    
2020
	-- Behaviour of component 'and_163' model 'and'
2021
	and_163 <=
2022
		sig_324 and
2023
		repeat(8, sig_233);
2024

    
2025
	-- Behaviour of component 'and_164' model 'and'
2026
	and_164 <=
2027
		sig_325 and
2028
		repeat(8, sig_232);
2029

    
2030
	-- Behaviour of component 'and_165' model 'and'
2031
	and_165 <=
2032
		sig_326 and
2033
		repeat(8, sig_231);
2034

    
2035
	-- Behaviour of component 'and_166' model 'and'
2036
	and_166 <=
2037
		sig_327 and
2038
		repeat(8, sig_230);
2039

    
2040
	-- Behaviour of component 'and_167' model 'and'
2041
	and_167 <=
2042
		sig_328 and
2043
		repeat(8, sig_229);
2044

    
2045
	-- Behaviour of component 'and_168' model 'and'
2046
	and_168 <=
2047
		sig_329 and
2048
		repeat(8, sig_228);
2049

    
2050
	-- Behaviour of component 'and_169' model 'and'
2051
	and_169 <=
2052
		sig_330 and
2053
		repeat(8, sig_227);
2054

    
2055
	-- Behaviour of component 'and_182' model 'and'
2056
	and_182 <=
2057
		sig_336 and
2058
		repeat(8, sig_321);
2059

    
2060
	-- Behaviour of component 'and_184' model 'and'
2061
	and_184 <=
2062
		sig_337 and
2063
		repeat(8, sig_320);
2064

    
2065
	-- Behaviour of component 'and_186' model 'and'
2066
	and_186 <=
2067
		sig_338 and
2068
		repeat(8, sig_290);
2069

    
2070
	-- Behaviour of component 'and_192' model 'and'
2071
	and_192 <=
2072
		not_122 and
2073
		sig_319;
2074

    
2075
	-- Behaviour of component 'and_194' model 'and'
2076
	and_194 <=
2077
		not_122 and
2078
		sig_318;
2079

    
2080
	-- Behaviour of component 'and_196' model 'and'
2081
	and_196 <=
2082
		not_122 and
2083
		sig_225;
2084

    
2085
	-- Behaviour of component 'mux_81' model 'mux'
2086
	mux_81 <=
2087
		(sig_259 and psc_loop_reg_3(0)) or
2088
		(sig_247 and augh_main_i(3)) or
2089
		(sig_245 and sig_298(3));
2090

    
2091
	-- Behaviour of component 'mux_82' model 'mux'
2092
	mux_82 <=
2093
		(sig_257 and and_116) or
2094
		(sig_246 and sig_315) or
2095
		(sig_244 and sig_311) or
2096
		(sig_266 and and_194) or
2097
		(sig_255 and '1');
2098

    
2099
	-- Behaviour of component 'mux_83' model 'mux'
2100
	mux_83 <=
2101
		(sig_259 and psc_loop_reg_3(0)) or
2102
		(sig_258 and sig_297(3)) or
2103
		(sig_271 and augh_main_i(3));
2104

    
2105
	-- Behaviour of component 'mux_84' model 'mux'
2106
	mux_84 <=
2107
		(repeat(8, sig_259) and cp_din(31 downto 24)) or
2108
		(repeat(8, sig_267) and augh_main_i(7 downto 0));
2109

    
2110
	-- Behaviour of component 'mux_85' model 'mux'
2111
	mux_85 <=
2112
		(sig_259 and psc_loop_reg_3(0)) or
2113
		(sig_247 and augh_main_i(3)) or
2114
		(sig_245 and sig_298(3));
2115

    
2116
	-- Behaviour of component 'mux_86' model 'mux'
2117
	mux_86 <=
2118
		(sig_257 and and_116) or
2119
		(sig_246 and sig_225) or
2120
		(sig_244 and sig_310) or
2121
		(sig_266 and and_196);
2122

    
2123
	-- Behaviour of component 'mux_87' model 'mux'
2124
	mux_87 <=
2125
		(sig_259 and psc_loop_reg_3(0)) or
2126
		(sig_258 and sig_297(3)) or
2127
		(sig_271 and augh_main_i(3));
2128

    
2129
	-- Behaviour of component 'mux_88' model 'mux'
2130
	mux_88 <=
2131
		(repeat(8, sig_259) and cp_din(39 downto 32)) or
2132
		(repeat(8, sig_267) and augh_main_i(7 downto 0));
2133

    
2134
	-- Behaviour of component 'mux_89' model 'mux'
2135
	mux_89 <=
2136
		(sig_259 and psc_loop_reg_3(0)) or
2137
		(sig_247 and augh_main_i(3)) or
2138
		(sig_245 and sig_298(3));
2139

    
2140
	-- Behaviour of component 'mux_90' model 'mux'
2141
	mux_90 <=
2142
		(sig_257 and and_116) or
2143
		(sig_246 and sig_314) or
2144
		(sig_244 and sig_309) or
2145
		(sig_266 and and_197);
2146

    
2147
	-- Behaviour of component 'mux_91' model 'mux'
2148
	mux_91 <=
2149
		(sig_259 and psc_loop_reg_3(0)) or
2150
		(sig_258 and sig_297(3)) or
2151
		(sig_271 and augh_main_i(3));
2152

    
2153
	-- Behaviour of component 'mux_92' model 'mux'
2154
	mux_92 <=
2155
		(repeat(8, sig_259) and cp_din(47 downto 40)) or
2156
		(repeat(8, sig_267) and augh_main_i(7 downto 0));
2157

    
2158
	-- Behaviour of component 'mux_93' model 'mux'
2159
	mux_93 <=
2160
		(sig_259 and psc_loop_reg_3(0)) or
2161
		(sig_247 and augh_main_i(3)) or
2162
		(sig_245 and sig_298(3));
2163

    
2164
	-- Behaviour of component 'mux_94' model 'mux'
2165
	mux_94 <=
2166
		(sig_257 and and_116) or
2167
		(sig_246 and sig_224) or
2168
		(sig_244 and sig_308) or
2169
		(sig_266 and and_199);
2170

    
2171
	-- Behaviour of component 'mux_95' model 'mux'
2172
	mux_95 <=
2173
		(sig_259 and psc_loop_reg_3(0)) or
2174
		(sig_258 and sig_297(3)) or
2175
		(sig_271 and augh_main_i(3));
2176

    
2177
	-- Behaviour of component 'mux_96' model 'mux'
2178
	mux_96 <=
2179
		(repeat(8, sig_259) and cp_din(55 downto 48)) or
2180
		(repeat(8, sig_267) and augh_main_i(7 downto 0));
2181

    
2182
	-- Behaviour of component 'mux_97' model 'mux'
2183
	mux_97 <=
2184
		(sig_259 and psc_loop_reg_3(0)) or
2185
		(sig_247 and augh_main_i(3)) or
2186
		(sig_245 and sig_298(3));
2187

    
2188
	-- Behaviour of component 'mux_98' model 'mux'
2189
	mux_98 <=
2190
		(sig_257 and and_116) or
2191
		(sig_246 and sig_313) or
2192
		(sig_244 and sig_307) or
2193
		(sig_266 and and_201);
2194

    
2195
	-- Behaviour of component 'mux_99' model 'mux'
2196
	mux_99 <=
2197
		(sig_259 and psc_loop_reg_3(0)) or
2198
		(sig_258 and sig_297(3)) or
2199
		(sig_271 and augh_main_i(3));
2200

    
2201
	-- Behaviour of component 'mux_100' model 'mux'
2202
	mux_100 <=
2203
		(repeat(8, sig_259) and cp_din(63 downto 56)) or
2204
		(repeat(8, sig_267) and augh_main_i(7 downto 0));
2205

    
2206
	-- Behaviour of component 'mux_101' model 'mux'
2207
	mux_101 <=
2208
		(sig_259 and psc_loop_reg_3(0)) or
2209
		(sig_247 and augh_main_i(3)) or
2210
		(sig_245 and sig_298(3));
2211

    
2212
	-- Behaviour of component 'mux_102' model 'mux'
2213
	mux_102 <=
2214
		(sig_257 and and_116) or
2215
		(sig_246 and sig_223) or
2216
		(sig_244 and sig_306) or
2217
		(sig_266 and and_203);
2218

    
2219
	-- Behaviour of component 'mux_103' model 'mux'
2220
	mux_103 <=
2221
		(sig_259 and psc_loop_reg_3(0)) or
2222
		(sig_258 and sig_297(3)) or
2223
		(sig_271 and augh_main_i(3));
2224

    
2225
	-- Behaviour of component 'mux_106' model 'mux'
2226
	mux_106 <=
2227
		(sig_239 and sig_301) or
2228
		(sig_238 and sig_316);
2229

    
2230
	-- Behaviour of component 'mux_108' model 'mux'
2231
	mux_108 <=
2232
		(sig_241 and sig_302);
2233

    
2234
	-- Behaviour of component 'mux_109' model 'mux'
2235
	mux_109 <=
2236
		(repeat(64, sig_263) and (sig_330 & sig_329 & sig_328 & sig_327 & sig_326 & sig_325 & sig_324 & sig_323)) or
2237
		(repeat(64, sig_259) and (sig_338 & sig_337 & sig_336 & sig_335 & sig_334 & sig_333 & sig_332 & sig_331)) or
2238
		(repeat(64, sig_251) and (psc_stuff_reg_11 & cp_id_reg_4));
2239

    
2240
	-- Behaviour of component 'mux_110' model 'mux'
2241
	mux_110 <=
2242
		(sig_265 and '1') or
2243
		(sig_263 and sig_305) or
2244
		(sig_259 and sig_317) or
2245
		(sig_251 and sig_280);
2246

    
2247
	-- Behaviour of component 'and_116' model 'and'
2248
	and_116 <=
2249
		cp_en and
2250
		cp_rest;
2251

    
2252
	-- Behaviour of component 'not_122' model 'not'
2253
	not_122 <= not (
2254
		cp_en
2255
	);
2256

    
2257
	-- Behaviour of component 'or_143' model 'or'
2258
	or_143 <=
2259
		and_144 or
2260
		and_155 or
2261
		and_157 or
2262
		and_159 or
2263
		and_147 or
2264
		and_149 or
2265
		and_151 or
2266
		and_153;
2267

    
2268
	-- Behaviour of component 'and_147' model 'and'
2269
	and_147 <=
2270
		sig_332 and
2271
		repeat(8, sig_233);
2272

    
2273
	-- Behaviour of component 'and_149' model 'and'
2274
	and_149 <=
2275
		sig_333 and
2276
		repeat(8, sig_232);
2277

    
2278
	-- Behaviour of component 'and_151' model 'and'
2279
	and_151 <=
2280
		sig_334 and
2281
		repeat(8, sig_231);
2282

    
2283
	-- Behaviour of component 'and_153' model 'and'
2284
	and_153 <=
2285
		sig_335 and
2286
		repeat(8, sig_230);
2287

    
2288
	-- Behaviour of component 'and_155' model 'and'
2289
	and_155 <=
2290
		sig_336 and
2291
		repeat(8, sig_229);
2292

    
2293
	-- Behaviour of component 'and_157' model 'and'
2294
	and_157 <=
2295
		sig_337 and
2296
		repeat(8, sig_228);
2297

    
2298
	-- Behaviour of component 'and_159' model 'and'
2299
	and_159 <=
2300
		sig_338 and
2301
		repeat(8, sig_227);
2302

    
2303
	-- Behaviour of component 'or_161' model 'or'
2304
	or_161 <=
2305
		and_162 or
2306
		and_167 or
2307
		and_168 or
2308
		and_169 or
2309
		and_163 or
2310
		and_164 or
2311
		and_165 or
2312
		and_166;
2313

    
2314
	-- Behaviour of component 'and_162' model 'and'
2315
	and_162 <=
2316
		sig_323 and
2317
		repeat(8, sig_296);
2318

    
2319
	-- Behaviour of component 'or_172' model 'or'
2320
	or_172 <=
2321
		and_173 or
2322
		and_182 or
2323
		and_184 or
2324
		and_186 or
2325
		and_175 or
2326
		and_177 or
2327
		and_179 or
2328
		and_181;
2329

    
2330
	-- Behaviour of component 'and_173' model 'and'
2331
	and_173 <=
2332
		sig_331 and
2333
		repeat(8, sig_294);
2334

    
2335
	-- Behaviour of component 'and_175' model 'and'
2336
	and_175 <=
2337
		sig_332 and
2338
		repeat(8, sig_293);
2339

    
2340
	-- Behaviour of component 'and_177' model 'and'
2341
	and_177 <=
2342
		sig_333 and
2343
		repeat(8, sig_292);
2344

    
2345
	-- Behaviour of component 'and_179' model 'and'
2346
	and_179 <=
2347
		sig_334 and
2348
		repeat(8, sig_291);
2349

    
2350
	-- Behaviour of component 'and_181' model 'and'
2351
	and_181 <=
2352
		sig_335 and
2353
		repeat(8, sig_314);
2354

    
2355
	-- Behaviour of component 'and_190' model 'and'
2356
	and_190 <=
2357
		not_122 and
2358
		sig_287;
2359

    
2360
	-- Behaviour of component 'and_197' model 'and'
2361
	and_197 <=
2362
		not_122 and
2363
		sig_286;
2364

    
2365
	-- Behaviour of component 'and_199' model 'and'
2366
	and_199 <=
2367
		not_122 and
2368
		sig_285;
2369

    
2370
	-- Behaviour of component 'and_201' model 'and'
2371
	and_201 <=
2372
		not_122 and
2373
		sig_284;
2374

    
2375
	-- Behaviour of component 'and_203' model 'and'
2376
	and_203 <=
2377
		not_122 and
2378
		sig_283;
2379

    
2380
	-- Behaviour of component 'or_205' model 'or'
2381
	or_205 <=
2382
		and_206 or
2383
		and_211 or
2384
		and_212 or
2385
		and_213 or
2386
		and_207 or
2387
		and_208 or
2388
		and_209 or
2389
		and_210;
2390

    
2391
	-- Behaviour of component 'and_206' model 'and'
2392
	and_206 <=
2393
		sig_323 and
2394
		repeat(8, sig_287);
2395

    
2396
	-- Behaviour of component 'and_207' model 'and'
2397
	and_207 <=
2398
		sig_324 and
2399
		repeat(8, sig_319);
2400

    
2401
	-- Behaviour of component 'and_208' model 'and'
2402
	and_208 <=
2403
		sig_325 and
2404
		repeat(8, sig_318);
2405

    
2406
	-- Behaviour of component 'and_209' model 'and'
2407
	and_209 <=
2408
		sig_326 and
2409
		repeat(8, sig_225);
2410

    
2411
	-- Behaviour of component 'and_210' model 'and'
2412
	and_210 <=
2413
		sig_327 and
2414
		repeat(8, sig_286);
2415

    
2416
	-- Behaviour of component 'and_211' model 'and'
2417
	and_211 <=
2418
		sig_328 and
2419
		repeat(8, sig_285);
2420

    
2421
	-- Behaviour of component 'and_212' model 'and'
2422
	and_212 <=
2423
		sig_329 and
2424
		repeat(8, sig_284);
2425

    
2426
	-- Behaviour of component 'and_213' model 'and'
2427
	and_213 <=
2428
		sig_330 and
2429
		repeat(8, sig_283);
2430

    
2431
	-- Behaviour of component 'and_144' model 'and'
2432
	and_144 <=
2433
		sig_331 and
2434
		repeat(8, sig_296);
2435

    
2436
	-- Behaviour of all components of model 'reg'
2437
	-- Registers with clock = sig_clock and reset = sig_reset active '1'
2438
	process(sig_clock, sig_reset)
2439
	begin
2440
		if sig_reset = '1' then
2441
			psc_stuff_reg_11 <= "0000000000000000000000000000000000000000000000000000000000000";
2442
		else
2443
			if rising_edge(sig_clock) then
2444
				if mux_20 = '1' then
2445
					psc_stuff_reg_11 <= augh_main_i & augh_main_result(31 downto 3);
2446
				end if;
2447
			end if;
2448
		end if;
2449
	end process;
2450
	-- Registers with clock = sig_clock and no reset
2451
	process(sig_clock)
2452
	begin
2453
		if rising_edge(sig_clock) then
2454
			if mux_27 = '1' then
2455
				cp_id_reg_stable_5 <= mux_26;
2456
			end if;
2457
			if mux_29 = '1' then
2458
				cp_id_reg_4 <= mux_28;
2459
			end if;
2460
			if mux_31 = '1' then
2461
				psc_loop_reg_3 <= mux_30;
2462
			end if;
2463
			if mux_65 = '1' then
2464
				augh_main_i <= mux_64;
2465
			end if;
2466
			if mux_67 = '1' then
2467
				augh_main_result <= mux_66;
2468
			end if;
2469
			if mux_69 = '1' then
2470
				augh_main_std_addition <= mux_68;
2471
			end if;
2472
			if mux_71 = '1' then
2473
				augh_main_max_iter <= mux_70;
2474
			end if;
2475
		end if;
2476
	end process;
2477

    
2478
	-- Remaining signal assignments
2479
	-- Those who are not assigned by component instantiation
2480

    
2481
	sig_clock <= clock;
2482
	sig_reset <= reset;
2483
	sig_start <= start;
2484
	test_cp_4_6 <= mux_25;
2485
	test_cp_3_7 <= mux_24;
2486
	test_cp_0_8 <= mux_23;
2487
	test_cp_1_9 <= mux_22;
2488
	memextrct_loop_sig_13 <= sig_303;
2489
	memextrct_loop_sig_14 <= sig_303;
2490
	sig_339 <= repeat(24, or_172(7)) & or_172;
2491
	sig_340 <= or_161(7) & or_161;
2492
	sig_341 <= or_143(7) & or_143;
2493
	sig_342 <= repeat(23, sig_295(8)) & sig_295;
2494

    
2495
	-- Remaining top-level ports assignments
2496
	-- Those who are not assigned by component instantiation
2497

    
2498
	stdin_rdy <= mux_106;
2499
	stdout_data <= augh_main_result;
2500
	stdout_rdy <= mux_108;
2501
	cp_dout <= mux_109;
2502
	cp_ok <= mux_110;
2503

    
2504
end architecture;