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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue50 / vector.d / assert_uut.vhd @ 3fd18385

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--test bench written by Alban Bourge @ TIMA
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.pkg_tb.all;
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entity assert_uut is
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	port(
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				clock        : in std_logic;
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				reset        : in std_logic;
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				context_uut  : in context_t;
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				en_feed      : in std_logic;
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				stdin_rdy    : in std_logic;
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				stdin_ack    : out std_logic;
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				stdin_data   : out stdin_vector;
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				en_check     : in std_logic;
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				stdout_rdy   : in std_logic;
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				stdout_ack   : out std_logic;
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				stdout_data  : in stdout_vector;
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				vecs_found   : out std_logic;
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				vec_read     : out std_logic;
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				n_error      : out std_logic
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			);
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end assert_uut;
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architecture rtl of assert_uut is
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	type vin_table  is array(0 to 2**VEC_NO_SIZE - 1) of stdin_vector;
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	type vout_table is array(0 to 2**VEC_NO_SIZE - 1) of stdout_vector;
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	constant input_vectors_1 : vin_table := (
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		--##INPUT_VECTORS_1_GO_DOWN_HERE##--
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		0 => x"00_00_00_07",
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		1 => x"00_00_00_03",
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		--##INPUT_VECTORS_1_GO_OVER_HERE##--
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		others => (others => '0'));
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	constant output_vectors_1 : vout_table := (
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		--##OUTPUT_VECTORS_1_GO_DOWN_HERE##--
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		0 => x"00_00_00_16",
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		--##OUTPUT_VECTORS_1_GO_OVER_HERE##--
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		others => (others => '0'));
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	constant input_vectors_2 : vin_table := (
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		--##INPUT_VECTORS_2_GO_DOWN_HERE##--
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		0 => x"00_00_00_07",
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		1 => x"00_00_00_03",
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		--##INPUT_VECTORS_2_GO_OVER_HERE##--
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		others => (others => '0'));
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	constant output_vectors_2 : vout_table := (
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		--##OUTPUT_VECTORS_2_GO_DOWN_HERE##--
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		0 => x"00_00_00_16",
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		--##OUTPUT_VECTORS_2_GO_OVER_HERE##--
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		others => (others => '0'));
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	signal out_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
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	signal out_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
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	signal stdin_ack_sig  : std_logic;
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	signal vector_read    : std_logic;
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begin
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	feed : process(reset, clock) is
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	variable in_vec_counter_1  : unsigned(VEC_NO_SIZE - 1 downto 0);
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	variable in_vec_counter_2  : unsigned(VEC_NO_SIZE - 1 downto 0);
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	begin
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		if (reset = '1') then
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			in_vec_counter_1 := (others => '0');
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			in_vec_counter_2 := (others => '0');
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			stdin_data       <= (others => '0');
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			stdin_ack_sig    <= '0';
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		elsif rising_edge(clock) then
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			case context_uut is
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				when "01" =>
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					if (en_feed = '1') then
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						stdin_data <= input_vectors_1(to_integer(in_vec_counter_1));
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						stdin_ack_sig  <= '1';
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						if (stdin_rdy = '1' and stdin_ack_sig = '1') then
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							in_vec_counter_1 := in_vec_counter_1 + 1;
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							stdin_ack_sig  <= '0';
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						end if;
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					else
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						--in_vec_counter_1 <= (others => '0');
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						stdin_data     <= (others => '0');
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						stdin_ack_sig  <= '0';
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					end if;
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				when "10" =>
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					if (en_feed = '1') then
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						stdin_data <= input_vectors_2(to_integer(in_vec_counter_2));
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						stdin_ack_sig  <= '1';
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						if (stdin_rdy = '1' and stdin_ack_sig = '1') then
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							in_vec_counter_2 := in_vec_counter_2 + 1;
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							stdin_ack_sig  <= '0';
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						end if;
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					else
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						--in_vec_counter_2 <= (others => '0');
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						stdin_data     <= (others => '0');
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						stdin_ack_sig  <= '0';
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					end if;
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				when others =>
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			end case;
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		end if;
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	end process feed;
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	check : process(reset, clock) is
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	begin
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		if (reset = '1') then
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			n_error     <= '1';
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			vec_read <= '0';
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		elsif rising_edge(clock) then
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			vec_read <= '0';
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			if (en_check = '1') then
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				if (stdout_rdy = '1') then
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					vec_read <= '1';
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					case context_uut is
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						when "01" =>
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							assert (stdout_data = output_vectors_1(to_integer(out_vec_counter_1)))
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							report "ERROR ---> Bad output vector found";
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							--synthesizable check
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							if (stdout_data /= output_vectors_1(to_integer(out_vec_counter_1))) then
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								n_error <= '0';
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							end if;
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						when "10" =>
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							assert (stdout_data = output_vectors_2(to_integer(out_vec_counter_2)))
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							report "ERROR ---> Bad output vector found";
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							--synthesizable check
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							if (stdout_data /= output_vectors_2(to_integer(out_vec_counter_2))) then
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								n_error <= '0';
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							end if;
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						when others =>
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					end case;
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				end if;
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			end if;
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		end if;
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	end process check;
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	read_counter : process(reset, clock) is
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	begin
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		if (reset = '1') then
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			out_vec_counter_1 <= (others => '0');
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			out_vec_counter_2 <= (others => '0');
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		elsif rising_edge(clock) then
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			if (en_check = '1') then
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				if (stdout_rdy = '1') then
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					case context_uut is
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						when "01" =>
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							out_vec_counter_1 <= out_vec_counter_1 + 1;
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						when "10" =>
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							out_vec_counter_2 <= out_vec_counter_2 + 1;
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						when others =>
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					end case;
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				end if;
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			--else
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			--	case context_uut is
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			--		when "01" =>
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			--			out_vec_counter_1 <= (others => '0');
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			--		when "10" =>
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			--			out_vec_counter_2 <= (others => '0');
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			--		when others =>
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			--	end case;
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			end if;
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		end if;
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	end process read_counter;
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	--asynchronous declarations
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	stdout_ack <= en_check;
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	stdin_ack <= stdin_ack_sig;
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	vecs_found <= '1' when (out_vec_counter_1 /= 0 or out_vec_counter_2 /= 0) else '0';
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end rtl;