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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue50 / idct.d / assert_uut.vhd @ 3fd18385

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--test bench written by Alban Bourge @ TIMA
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.pkg_tb.all;
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entity assert_uut is
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	port(
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				clock        : in std_logic;
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				reset        : in std_logic;
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				context_uut  : in context_t;
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				en_feed      : in std_logic;
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				stdin_rdy    : in std_logic;
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				stdin_ack    : out std_logic;
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				stdin_data   : out stdin_vector;
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				en_check     : in std_logic;
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				stdout_rdy   : in std_logic;
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				stdout_ack   : out std_logic;
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				stdout_data  : in stdout_vector;
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				vecs_found   : out std_logic;
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				vec_read     : out std_logic;
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				n_error      : out std_logic
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			);
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end assert_uut;
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architecture rtl of assert_uut is
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30
	type vin_table  is array(0 to 2**VEC_NO_SIZE - 1) of stdin_vector;
31
	type vout_table is array(0 to 2**VEC_NO_SIZE - 1) of stdout_vector;
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	constant input_vectors_1 : vin_table := (
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		--##INPUT_VECTORS_1_GO_DOWN_HERE##--
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		0 => x"00_00_00_a3",
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		1 => x"00_00_00_ea",
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		2 => x"00_00_00_cc",
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		3 => x"00_00_00_28",
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		4 => x"00_00_00_30",
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		5 => x"00_00_00_a0",
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		6 => x"00_00_00_c0",
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		7 => x"00_00_00_80",
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		8 => x"00_00_00_00",
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		9 => x"00_00_00_00",
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		10 => x"00_00_00_00",
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		11 => x"00_00_00_00",
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		12 => x"00_00_00_00",
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		13 => x"00_00_00_00",
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		14 => x"00_00_00_00",
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		15 => x"00_00_00_00",
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		16 => x"00_00_00_00",
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		17 => x"00_00_00_00",
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		18 => x"00_00_00_00",
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		19 => x"00_00_00_00",
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		20 => x"00_00_00_00",
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		21 => x"00_00_00_00",
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		22 => x"00_00_00_00",
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		23 => x"00_00_00_00",
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		24 => x"00_00_00_00",
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		25 => x"00_00_00_00",
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		26 => x"00_00_00_00",
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		27 => x"00_00_00_00",
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		28 => x"00_00_00_00",
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		29 => x"00_00_00_00",
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		30 => x"00_00_00_00",
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		31 => x"00_00_00_00",
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		32 => x"00_00_00_00",
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		33 => x"00_00_00_00",
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		34 => x"00_00_00_00",
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		35 => x"00_00_00_00",
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		36 => x"00_00_00_00",
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		37 => x"00_00_00_00",
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		38 => x"00_00_00_00",
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		39 => x"00_00_00_00",
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		40 => x"00_00_00_00",
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		41 => x"00_00_00_00",
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		42 => x"00_00_00_00",
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		43 => x"00_00_00_00",
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		44 => x"00_00_00_00",
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		45 => x"00_00_00_00",
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		46 => x"00_00_00_00",
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		47 => x"00_00_00_00",
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		48 => x"00_00_00_00",
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		49 => x"00_00_00_00",
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		50 => x"00_00_00_00",
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		51 => x"00_00_00_00",
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		52 => x"00_00_00_00",
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		53 => x"00_00_00_00",
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		54 => x"00_00_00_00",
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		55 => x"00_00_00_00",
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		56 => x"00_00_00_00",
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		57 => x"00_00_00_00",
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		58 => x"00_00_00_00",
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		59 => x"00_00_00_00",
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		60 => x"00_00_00_00",
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		61 => x"00_00_00_00",
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		62 => x"00_00_00_00",
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		63 => x"00_00_00_00",
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		--##INPUT_VECTORS_1_GO_OVER_HERE##--
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		others => (others => '0'));
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	constant output_vectors_1 : vout_table := (
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		--##OUTPUT_VECTORS_1_GO_DOWN_HERE##--
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		0 => x"ff",
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		1 => x"00",
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		2 => x"ff",
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		3 => x"ff",
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		4 => x"00",
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		5 => x"00",
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		6 => x"ff",
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		7 => x"00",
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		8 => x"ff",
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		9 => x"00",
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		10 => x"ff",
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		11 => x"ff",
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		12 => x"00",
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		13 => x"00",
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		14 => x"ff",
117
		15 => x"00",
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		16 => x"ff",
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		17 => x"00",
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		18 => x"ff",
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		19 => x"ff",
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		20 => x"00",
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		21 => x"00",
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		22 => x"ff",
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		23 => x"00",
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		24 => x"ff",
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		25 => x"00",
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		26 => x"ff",
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		27 => x"ff",
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		28 => x"00",
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		29 => x"00",
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		30 => x"ff",
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		31 => x"00",
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		32 => x"ff",
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		33 => x"00",
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		34 => x"ff",
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		35 => x"ff",
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		36 => x"00",
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		37 => x"00",
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		38 => x"ff",
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		39 => x"00",
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		40 => x"ff",
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		41 => x"00",
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		42 => x"ff",
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		43 => x"ff",
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		44 => x"00",
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		45 => x"00",
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		46 => x"ff",
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		47 => x"00",
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		48 => x"ff",
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		49 => x"00",
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		50 => x"ff",
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		51 => x"ff",
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		52 => x"00",
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		53 => x"00",
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		54 => x"ff",
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		55 => x"00",
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		56 => x"ff",
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		57 => x"00",
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		58 => x"ff",
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		59 => x"ff",
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		60 => x"00",
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		61 => x"00",
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		62 => x"ff",
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		63 => x"00",
166
		--##OUTPUT_VECTORS_1_GO_OVER_HERE##--
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		others => (others => '0'));
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	constant input_vectors_2 : vin_table := (
169
		--##INPUT_VECTORS_2_GO_DOWN_HERE##--
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		0 => x"00_00_00_a3",
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		1 => x"00_00_00_ea",
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		2 => x"00_00_00_cc",
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		3 => x"00_00_00_28",
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		4 => x"00_00_00_30",
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		5 => x"00_00_00_a0",
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		6 => x"00_00_00_c0",
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		7 => x"00_00_00_80",
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		8 => x"00_00_00_00",
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		9 => x"00_00_00_00",
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		10 => x"00_00_00_00",
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		11 => x"00_00_00_00",
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		12 => x"00_00_00_00",
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		13 => x"00_00_00_00",
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		14 => x"00_00_00_00",
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		15 => x"00_00_00_00",
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		16 => x"00_00_00_00",
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		17 => x"00_00_00_00",
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		18 => x"00_00_00_00",
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		19 => x"00_00_00_00",
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		20 => x"00_00_00_00",
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		21 => x"00_00_00_00",
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		22 => x"00_00_00_00",
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		23 => x"00_00_00_00",
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		24 => x"00_00_00_00",
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		25 => x"00_00_00_00",
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		26 => x"00_00_00_00",
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		27 => x"00_00_00_00",
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		28 => x"00_00_00_00",
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		29 => x"00_00_00_00",
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		30 => x"00_00_00_00",
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		31 => x"00_00_00_00",
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		32 => x"00_00_00_00",
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		33 => x"00_00_00_00",
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		34 => x"00_00_00_00",
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		35 => x"00_00_00_00",
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		36 => x"00_00_00_00",
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		37 => x"00_00_00_00",
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		38 => x"00_00_00_00",
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		39 => x"00_00_00_00",
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		40 => x"00_00_00_00",
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		41 => x"00_00_00_00",
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		42 => x"00_00_00_00",
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		43 => x"00_00_00_00",
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		44 => x"00_00_00_00",
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		45 => x"00_00_00_00",
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		46 => x"00_00_00_00",
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		47 => x"00_00_00_00",
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		48 => x"00_00_00_00",
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		49 => x"00_00_00_00",
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		50 => x"00_00_00_00",
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		51 => x"00_00_00_00",
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		52 => x"00_00_00_00",
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		53 => x"00_00_00_00",
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		54 => x"00_00_00_00",
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		55 => x"00_00_00_00",
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		56 => x"00_00_00_00",
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		57 => x"00_00_00_00",
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		58 => x"00_00_00_00",
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		59 => x"00_00_00_00",
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		60 => x"00_00_00_00",
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		61 => x"00_00_00_00",
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		62 => x"00_00_00_00",
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		63 => x"00_00_00_00",
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		--##INPUT_VECTORS_2_GO_OVER_HERE##--
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		others => (others => '0'));
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	constant output_vectors_2 : vout_table := (
237
		--##OUTPUT_VECTORS_2_GO_DOWN_HERE##--
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		0 => x"ff",
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		1 => x"00",
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		2 => x"ff",
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		3 => x"ff",
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		4 => x"00",
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		5 => x"00",
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		6 => x"ff",
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		7 => x"00",
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		8 => x"ff",
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		9 => x"00",
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		10 => x"ff",
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		11 => x"ff",
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		12 => x"00",
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		13 => x"00",
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		14 => x"ff",
253
		15 => x"00",
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		16 => x"ff",
255
		17 => x"00",
256
		18 => x"ff",
257
		19 => x"ff",
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		20 => x"00",
259
		21 => x"00",
260
		22 => x"ff",
261
		23 => x"00",
262
		24 => x"ff",
263
		25 => x"00",
264
		26 => x"ff",
265
		27 => x"ff",
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		28 => x"00",
267
		29 => x"00",
268
		30 => x"ff",
269
		31 => x"00",
270
		32 => x"ff",
271
		33 => x"00",
272
		34 => x"ff",
273
		35 => x"ff",
274
		36 => x"00",
275
		37 => x"00",
276
		38 => x"ff",
277
		39 => x"00",
278
		40 => x"ff",
279
		41 => x"00",
280
		42 => x"ff",
281
		43 => x"ff",
282
		44 => x"00",
283
		45 => x"00",
284
		46 => x"ff",
285
		47 => x"00",
286
		48 => x"ff",
287
		49 => x"00",
288
		50 => x"ff",
289
		51 => x"ff",
290
		52 => x"00",
291
		53 => x"00",
292
		54 => x"ff",
293
		55 => x"00",
294
		56 => x"ff",
295
		57 => x"00",
296
		58 => x"ff",
297
		59 => x"ff",
298
		60 => x"00",
299
		61 => x"00",
300
		62 => x"ff",
301
		63 => x"00",
302
		--##OUTPUT_VECTORS_2_GO_OVER_HERE##--
303
		others => (others => '0'));
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	signal in_vec_counter_1  : unsigned(VEC_NO_SIZE - 1 downto 0);
305
	signal in_vec_counter_2  : unsigned(VEC_NO_SIZE - 1 downto 0);
306
	signal out_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
307
	signal out_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
308

    
309
	signal stdin_ack_sig  : std_logic;
310
	signal vector_read    : std_logic;
311

    
312
begin
313

    
314
	feed : process(reset, clock) is
315
	begin
316
		if (reset = '1') then
317
			in_vec_counter_1 <= (others => '0');
318
			in_vec_counter_2 <= (others => '0');
319
			stdin_data       <= (others => '0');
320
			stdin_ack_sig    <= '0';
321
		elsif rising_edge(clock) then
322
			case context_uut is
323
				when "01" =>
324
					if (en_feed = '1') then
325
						stdin_data <= input_vectors_1(to_integer(in_vec_counter_1));
326
						stdin_ack_sig  <= '1';
327
						if (stdin_rdy = '1' and stdin_ack_sig = '1') then
328
							in_vec_counter_1 <= in_vec_counter_1 + 1;
329
							stdin_ack_sig  <= '0';
330
						end if;
331
					else
332
						--in_vec_counter_1 <= (others => '0');
333
						stdin_data     <= (others => '0');
334
						stdin_ack_sig  <= '0';
335
					end if;
336
				when "10" =>
337
					if (en_feed = '1') then
338
						stdin_data <= input_vectors_2(to_integer(in_vec_counter_2));
339
						stdin_ack_sig  <= '1';
340
						if (stdin_rdy = '1' and stdin_ack_sig = '1') then
341
							in_vec_counter_2 <= in_vec_counter_2 + 1;
342
							stdin_ack_sig  <= '0';
343
						end if;
344
					else
345
						--in_vec_counter_2 <= (others => '0');
346
						stdin_data     <= (others => '0');
347
						stdin_ack_sig  <= '0';
348
					end if;
349
				when others =>
350
			end case;
351
		end if;
352
	end process feed;
353

    
354
	check : process(reset, clock) is
355
	begin
356
		if (reset = '1') then
357
			n_error     <= '1';
358
			vec_read <= '0';
359
		elsif rising_edge(clock) then
360
			vec_read <= '0';
361
			if (en_check = '1') then
362
				if (stdout_rdy = '1') then
363
					vec_read <= '1';
364
					case context_uut is
365
						when "01" =>
366
							assert (stdout_data = output_vectors_1(to_integer(out_vec_counter_1)))
367
							report "ERROR ---> Bad output vector found";
368
							--synthesizable check
369
							if (stdout_data /= output_vectors_1(to_integer(out_vec_counter_1))) then
370
								n_error <= '0';
371
							end if;
372
						when "10" =>
373
							assert (stdout_data = output_vectors_2(to_integer(out_vec_counter_2)))
374
							report "ERROR ---> Bad output vector found";
375
							--synthesizable check
376
							if (stdout_data /= output_vectors_2(to_integer(out_vec_counter_2))) then
377
								n_error <= '0';
378
							end if;
379
						when others =>
380
					end case;
381
				end if;
382
			end if;
383
		end if;
384
	end process check;
385

    
386
	read_counter : process(reset, clock) is
387
	begin
388
		if (reset = '1') then
389
			out_vec_counter_1 <= (others => '0');
390
			out_vec_counter_2 <= (others => '0');
391
		elsif rising_edge(clock) then
392
			if (en_check = '1') then
393
				if (stdout_rdy = '1') then
394
					case context_uut is
395
						when "01" =>
396
							out_vec_counter_1 <= out_vec_counter_1 + 1;
397
						when "10" =>
398
							out_vec_counter_2 <= out_vec_counter_2 + 1;
399
						when others =>
400
					end case;
401
				end if;
402
			--else
403
			--	case context_uut is
404
			--		when "01" =>
405
			--			out_vec_counter_1 <= (others => '0');
406
			--		when "10" =>
407
			--			out_vec_counter_2 <= (others => '0');
408
			--		when others =>
409
			--	end case;
410
			end if;
411
		end if;
412
	end process read_counter;
413

    
414
	--asynchronous declarations
415
	stdout_ack <= en_check;
416
	stdin_ack <= stdin_ack_sig;
417
	vecs_found <= '1' when (out_vec_counter_1 /= 0 or out_vec_counter_2 /= 0) else '0';
418

    
419
end rtl;