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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue256 / testcase_testbench.json @ 3fd18385

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "testcase_testbench"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "bench"], "entity" : ["IDENTIFIER", "testcase_testbench"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "clk"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "bit"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "dut"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "testcase"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "empty"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
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          ]}
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        ], ["PROCESS_STATEMENT", {
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          "id" : ["IDENTIFIER", "stimulus"], "PROCESS_STATEMENT_PART" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "clk"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'0'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "clk"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'1'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "clk"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'1'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "clk"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'0'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "clk"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'1'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"]]}
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        ]]}
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      ]}
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    ]}
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  }