Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue256 / testcase2_testbench.vhd @ 3fd18385

History | View | Annotate | Download (704 Bytes)

1
entity testcase2_testbench is
2
end entity testcase2_testbench;
3

    
4
architecture bench of testcase2_testbench is
5
    signal clk: bit;
6
begin
7
    dut: entity work.testcase2(empty) port map(clk => clk);
8

    
9
    stimulus: process is
10
    begin
11
        -- Valid low and high pulses
12
        clk <= '0';
13
        wait for 10 ns;
14
        clk <= '1';
15
        wait for 10 ns;
16
        -- Confirm that we're timing events, not transactions
17
        clk <= '1';
18
        wait for 5 ns;
19
        -- Now send a short pulse to make the assertion fire        
20
        clk <= '0';
21
        wait for 5 ns;
22
        -- Assertion should fire here, at 30ns
23
        clk <= '1';
24
        wait;
25
    end process stimulus;
26
end architecture bench;