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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug23165 / mwe_failing / counter.vhd @ 3fd18385

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-- counter
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-- clk: clock input
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-- en: enable input
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-- rst: reset input
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-- dir: direction pin (1 = up, 0 = down)
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-- q: output
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity counter is
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	generic (
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		width	: positive := 16
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	);
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	port (
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		clk	: in std_logic;
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		q	: out std_logic_vector(width-1 downto 0)
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	);
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end counter;
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architecture behav of counter is
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signal cnt	: unsigned(width-1 downto 0) := to_unsigned(0, width);
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begin
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	process
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	begin
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		wait until rising_edge(clk);
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		cnt <= cnt + to_unsigned(1, cnt'length);
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	end process;
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	q <= std_logic_vector(cnt);
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end behav;
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