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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug043 / sha256.vhd @ 3fd18385

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library ieee;
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use     ieee.std_logic_1164.all;
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use     ieee.numeric_std.all;
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--use IEEE.std_logic_unsigned.all;
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ENTITY sha256forBTC is
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    Port ( reset 	: in  STD_LOGIC;
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           clock 	: in  STD_LOGIC;
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           --data input signals
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           data 	: in  STD_LOGIC_VECTOR (511 downto 0);
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           enable : in  STD_LOGIC;
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           busy   : out STD_LOGIC;
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           --hash output signals
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           digest	: out STD_LOGIC_VECTOR (255 downto 0);
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           ready 	: out STD_LOGIC);
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end sha256forBTC;
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ARCHITECTURE Behavioral of sha256forBTC is
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   type hT is array (0 to 7) of STD_LOGIC_VECTOR(31 downto 0);
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   constant hInit : hT :=
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     (x"6a09e667", x"bb67ae85", x"3c6ef372", x"a54ff53a", x"510e527f", x"9b05688c", x"1f83d9ab", x"5be0cd19");
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   type kT is array (0 to 63) of STD_LOGIC_VECTOR(31 downto 0);
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   constant k : kT :=
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     (x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
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      x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
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      x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
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      x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
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      x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
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      x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
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      x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
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      x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2");
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   signal a,b,c,d,e,f,g,h,h0,h1,h2,h3,h4,h5,h6,h7,s0,s1,su0,su1,maj,ch,temp1,temp2 : STD_LOGIC_VECTOR(31 downto 0);
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   type wT is array (15 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
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   signal w : wT;
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   signal wCNT, chunkCNT : STD_LOGIC_VECTOR(6 downto 0);
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   signal intEnable : STD_LOGIC;
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BEGIN
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   fsm: process(clock)
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   begin
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      if rising_edge(clock) then
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         if reset = '1' then
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            chunkCNT <= "1000000";
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         else
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            if chunkCNT = "1000000" then
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               if enable = '1' then
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                  chunkCNT <= "0000000";
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               end if;
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            else
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               chunkCNT <= std_logic_vector(unsigned(chunkCNT) + 1);
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            end if;
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         end if;
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      ready <= not intEnable;
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      end if;
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   end process;
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   intEnable <= not chunkCNT(6);
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   busy <= intEnable;
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   extension_pipe: process(clock)
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   begin
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      if rising_edge(clock) then
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         if enable = '1' then
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            w(0) <= data(31 downto 0);
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            w(1) <= data(63 downto 32);
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            w(2) <= data(95 downto 64);
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            w(3) <= data(127 downto 96);
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            w(4) <= data(159 downto 128);
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            w(5) <= data(191 downto 160);
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            w(6) <= data(223 downto 192);
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            w(7) <= data(255 downto 224);
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            w(8) <= data(287 downto 256);
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            w(9) <= data(319 downto 288);
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            w(10) <= data(351 downto 320);
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            w(11) <= data(383 downto 352);
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            w(12) <= data(415 downto 384);
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            w(13) <= data(447 downto 416);
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            w(14) <= data(479 downto 448);
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            w(15) <= data(511 downto 480);
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         elsif intEnable = '1' then
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	 w <= w(14 downto 0) & std_logic_vector(unsigned(w(15)) + unsigned(s0) + unsigned(w(6)) + unsigned(s1));
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         end if;
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      end if;
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   end process;
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   --extension_pipe asynchron circuitry
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   s0 <= (w(14)(6 downto 0) & w(14)(31 downto 7)) xor (w(14)(17 downto 0) & w(14)(31 downto 18)) xor ("000" & w(14)(31 downto 3));
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   s1 <= (w(1)(16 downto 0) & w(1)(31 downto 17)) xor (w(1)(18 downto 0) & w(1)(31 downto 19)) xor ("0000000000" & w(1)(31 downto 10));
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   --end of extension_pipe asynchron circuitry
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   main_loop_pipe: process(clock)
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   begin
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      if rising_edge(clock) then
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         if reset = '1' then
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            a <= hInit(0);
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            b <= hInit(1);
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            c <= hInit(2);
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            d <= hInit(3);
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            e <= hInit(4);
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            f <= hInit(5);
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            g <= hInit(6);
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            h <= hInit(7);
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         elsif intEnable = '0' then
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            a <= std_logic_vector(unsigned(h0) + unsigned(a));
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            b <= std_logic_vector(unsigned(h1) + unsigned(b));
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            c <= std_logic_vector(unsigned(h2) + unsigned(c));
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            d <= std_logic_vector(unsigned(h3) + unsigned(d));
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            e <= std_logic_vector(unsigned(h4) + unsigned(e));
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            f <= std_logic_vector(unsigned(h5) + unsigned(f));
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            g <= std_logic_vector(unsigned(h6) + unsigned(g));
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            h <= std_logic_vector(unsigned(h7) + unsigned(h));
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         else
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            h <= g;
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            g <= f;
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            f <= e;
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            e <= std_logic_vector(unsigned(d) + unsigned(temp1));
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            d <= c;
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            c <= b;
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            b <= a;
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            a <= temp2;
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         end if;
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      end if;
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   end process;
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   --main_loop_pipe asynchron circuitry
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   su1   <= (e(5 downto 0) & e(31 downto 6)) xor (e(10 downto 0) & e(31 downto 11)) xor (e(24 downto 0) & e(31 downto 25));
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   ch    <= (e and f) xor ((not e) and g);
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   temp1 <= std_logic_vector(unsigned(h) + 
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	    unsigned(su1) + 
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	    unsigned(ch) + 
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	    unsigned(k(to_integer(unsigned(chunkCNT(5 downto 0))))) + 
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	    unsigned(w(15)));
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   su0   <= (a(1 downto 0) & a(31 downto 2)) xor (a(12 downto 0) & a(31 downto 13)) xor (a(21 downto 0) & a(31 downto 22));
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   maj   <= (a and (b xor c)) xor (b and c);
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   temp2 <= std_logic_vector(unsigned(temp1) + unsigned(su0) + unsigned(maj));
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   --end of main_loop_pipe asynchron circuitry
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   add_hash_chunk: process(clock)
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   begin
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      if rising_edge(clock) then
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         if reset = '1' then
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            h0 <= x"00000000";
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            h1 <= x"00000000";
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            h2 <= x"00000000";
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            h3 <= x"00000000";
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            h4 <= x"00000000";
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            h5 <= x"00000000";
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            h6 <= x"00000000";
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            h7 <= x"00000000";
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         else
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            if intEnable = '0' then
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               h0 <= std_logic_vector(unsigned(h0) + unsigned(a));
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               h1 <= std_logic_vector(unsigned(h1) + unsigned(b));
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               h2 <= std_logic_vector(unsigned(h2) + unsigned(c));
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               h3 <= std_logic_vector(unsigned(h3) + unsigned(d));
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               h4 <= std_logic_vector(unsigned(h4) + unsigned(e));
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               h5 <= std_logic_vector(unsigned(h5) + unsigned(f));
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               h6 <= std_logic_vector(unsigned(h6) + unsigned(g));
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               h7 <= std_logic_vector(unsigned(h7) + unsigned(h));
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            end if;
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         end if;
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      end if;
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   end process;
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   digest <= h0 & h1 & h2 & h3 & h4 & h5 & h6 & h7;
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end Behavioral;