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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug021 / tb_cosim.vhd @ 3fd18385

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-- Company:      Dossmatik GmbH
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-- Create Date:   21:08:31 05/17/2011
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-- Target Device:  
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-- Tool versions:  
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-- Description:   
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-- 
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-- VHDL Test Bench 
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-- test for VHPI
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.sim_pkg.all;
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entity tb_cosim is
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end tb_cosim;
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architecture behavior of tb_cosim is
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 function crc (crc_value : std_logic_vector(31 downto 0)
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                          ) return std_logic_vector is
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    variable crc_out : std_logic_vector(31 downto 0);
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  begin
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    crc_out := (crc(3 downto 0)& crc_out(31 downto 4)) xor crc;
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    return crc_out;
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  end crc;
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  signal random : std_logic_vector ( 31 downto 0):=X"00000000";
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  -- Clock period definitions
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  constant board_clk_period : time := 20 ns;
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  signal board_clk: std_logic;
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begin
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  process (board_clk)
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  begin 
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    if rising_edge(board_clk) then
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      street(to_integer(unsigned(random)));
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      random<=crc(random);
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    end if;
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  end process;
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  -- Clock process definitions
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  board_clk_process : process
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  begin
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    board_clk <= '0';
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    wait for board_clk_period/2;
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      board_clk <= '1';
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    wait for board_clk_period/2;
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  end process;
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  end;