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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / best-chronometer-ever / test / simple_sim.vhd @ 3fd18385

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--------------------------------------------------------------------------------
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-- SIMPLE TEST -----------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- This test bench is meant to ensure the proper behavior of our chronometer.
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-- To avoid ridiculously long test runtimes, the Centisecond Timer should be
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-- set so it considers there are 8 clock cycles per centisecond. Similarly,
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-- the Display Manager's clock cycle target should be set to 2.
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-- The 59.99s limit should then be reached after around 959 900 ns.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity simple_sim is
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end simple_sim;
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architecture behavior of simple_sim is
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   -- Constants ----------------------------------------------------------------
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   constant display_value_0: std_logic_vector(6 downto 0) := B"0000001";
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   constant display_value_1: std_logic_vector(6 downto 0) := B"1001111";
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   constant display_value_2: std_logic_vector(6 downto 0) := B"0010010";
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   constant display_value_3: std_logic_vector(6 downto 0) := B"0000110";
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   constant display_value_4: std_logic_vector(6 downto 0) := B"1001100";
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   constant display_value_5: std_logic_vector(6 downto 0) := B"0100100";
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   constant display_value_6: std_logic_vector(6 downto 0) := B"0100000";
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   constant display_value_7: std_logic_vector(6 downto 0) := B"0001111";
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   constant display_value_8: std_logic_vector(6 downto 0) := B"0000000";
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   constant display_value_9: std_logic_vector(6 downto 0) := B"0000100";
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   constant display_value_error: std_logic_vector(6 downto 0) := B"0110000";
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   constant miniclock_period : time := 20 ns;
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   -- Signals ------------------------------------------------------------------
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   ---- Inputs -----------------------------------------------------------------
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   signal CK_50MHz:        std_logic := '0';
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   signal reset:           std_logic := '0';
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   signal BP_RAZ:          std_logic := '0';
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   signal BP_START_STOP:   std_logic := '0';
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 	---- Outputs ----------------------------------------------------------------
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   signal Display:   std_logic_vector(6 downto 0);
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   signal AN:        std_logic_vector(3 downto 0);
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   -- Natural representation of Display. 10 means "error".
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   signal Display_N: natural range 0 to 10;
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   -- Components ---------------------------------------------------------------
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   component best_chronometer_ever is
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      port
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      (
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         i_clock:       in std_logic;
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         i_reset:       in std_logic;
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         i_start_bp:    in std_logic;
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         i_raz_bp:      in std_logic;
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         o_display:     out std_logic_vector (6 downto 0);
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         o_an:          out std_logic_vector (3 downto 0)
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      );
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   end component;
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   -- Functions ----------------------------------------------------------------
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   function display_value_to_numeral (D: std_logic_vector(6 downto 0))
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      return natural is
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   begin
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      case D is
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         when display_value_0 => return 0;
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         when display_value_1 => return 1;
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         when display_value_2 => return 2;
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         when display_value_3 => return 3;
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         when display_value_4 => return 4;
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         when display_value_5 => return 5;
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         when display_value_6 => return 6;
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         when display_value_7 => return 7;
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         when display_value_8 => return 8;
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         when display_value_9 => return 9;
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         when others => return 10;
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      end case;
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   end display_value_to_numeral;
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begin
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   -- Unit Under Test ----------------------------------------------------------
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   uut: best_chronometer_ever
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   port map
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   (
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      i_clock => CK_50MHZ,
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      i_reset => reset,
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      i_start_bp => BP_START_STOP,
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      i_raz_bp => BP_RAZ,
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      o_display => Display,
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      o_an => AN
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   );
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   Display_N <= display_value_to_numeral(Display);
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   -- Clock Process ------------------------------------------------------------
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   miniclock_process: process
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   begin
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      CK_50MHz <= '0';
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      wait for (miniclock_period / 2);
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      CK_50MHz <= '1';
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      wait for (miniclock_period / 2);
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   end process;
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   -- Stimulus Process ---------------------------------------------------------
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   stim_proc: process
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   begin
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      reset         <= '1';
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      wait for 50 ns;
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      reset         <= '0';
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      wait for 50 ns;
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      BP_START_STOP <= '0';
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      BP_RAZ <= '0';
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      wait for 100 ns;
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      BP_START_STOP <= '1';
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      wait for 100 ns;
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      BP_START_STOP <= '0';
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      wait for 10000 ns;
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      BP_START_STOP <= '1';
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      wait for 100 ns;
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      BP_START_STOP <= '0';
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      wait for 400 ns;
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      BP_RAZ <= '1';
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      wait for 100 ns;
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      BP_RAZ <= '0';
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      wait for 400 ns;
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      BP_START_STOP <= '1';
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      wait for 100 ns;
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      BP_START_STOP <= '0';
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     assert false report "End of Test" severity note;
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     wait;
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   end process;
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end;