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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / STD_07100_bad.vhd @ 3fd18385

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-- Company   : CNES
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-- Author    : Mickael Carl (CNES)
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-- Copyright : Copyright (c) CNES.
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-- Licensing : GNU GPLv3
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-- Version         : V1
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-- Version history :
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--    V1 : 2015-04-10 : Mickael Carl (CNES): Creation
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-------------------------------------------------------------------------------------------------
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-- File name          : STD_07100_bad.vhd
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-- File Creation date : 2015-04-10
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-- Project name       : VHDL Handbook CNES Edition
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-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
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-- Description : Handbook example: Simulation ending: bad example
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--
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-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
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--               demonstrating good practices in VHDL and as such, its design is minimalistic.
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--               It is provided as is, without any warranty.
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--               This example is compliant with the Handbook version 1.
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--
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-------------------------------------------------------------------------------------------------
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-- Naming conventions:
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--
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-- i_Port: Input entity port
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-- o_Port: Output entity port
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-- b_Port: Bidirectional entity port
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-- g_My_Generic: Generic entity port
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--
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-- c_My_Constant: Constant definition
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-- t_My_Type: Custom type definition
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--
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-- My_Signal_n: Active low signal
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-- v_My_Variable: Variable
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-- sm_My_Signal: FSM signal
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-- pkg_Param: Element Param coming from a package
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--
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-- My_Signal_re: Rising edge detection of My_Signal
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-- My_Signal_fe: Falling edge detection of My_Signal
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-- My_Signal_rX: X times registered My_Signal signal
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--
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-- P_Process_Name: Process
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity STD_07100_bad is
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end STD_07100_bad;
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architecture Simulation of STD_07100_bad is
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   -- All signals for tested modules inputs/outputs
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   signal Clock    : std_logic := '0';
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   signal Reset_n  : std_logic;
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   signal D_Signal : std_logic;
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   signal Q_Signal : std_logic;
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   component DFlipFlop
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      port (
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         i_Clock   : in  std_logic;     -- Clock signal
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         i_Reset_n : in  std_logic;     -- Reset signal
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         i_D       : in  std_logic;     -- D Flip-Flop input signal
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         o_Q       : out std_logic;     -- D Flip-Flop output signal
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         o_Q_n     : out std_logic      -- D Flip-Flop output signal, inverted
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         );
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   end component;
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begin
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   -- The D Flip-Flop to test
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   T_DFlipFlop : DFlipFlop
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      port map (
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         i_Clock   => Clock,
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         i_Reset_n => Reset_n,
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         i_D       => D_Signal,
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         o_Q       => Q_Signal,
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         o_Q_n     => open
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         );
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   --CODE
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   -- Clock process
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   P_Clock : process
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   begin
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      Clock <= not Clock after 5 ns;
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   end process;
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   -- Test process
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   P_Test : process
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   begin
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      Reset_n  <= '0';
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      D_Signal <= '0';
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      wait until rising_edge(Clock);
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      Reset_n  <= '1';
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      wait until rising_edge(Clock);
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      D_Signal <= '1';
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      wait until rising_edge(Clock);
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      D_Signal <= '0';
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      wait;
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   end process;
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--CODE
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end Simulation;