lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / STD_07100_bad.json @ 3fd18385
History | View | Annotate | Download (7.22 KB)
1 |
{ |
---|---|
2 |
"DESIGN_FILE" : {
|
3 |
"design_units" : [{
|
4 |
"contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "IEEE"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "IEEE"], ["SIMPLE_NAME", "std_logic_1164"]]]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "IEEE"], ["SIMPLE_NAME", "numeric_std"]]]]]], "library" : ["ENTITY_DECLARATION", { |
5 |
"name" : ["IDENTIFIER", "STD_07100_bad"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []} |
6 |
]} |
7 |
, { |
8 |
"contexts" : [], "library" : ["ARCHITECTURE_BODY", { |
9 |
"name" : ["IDENTIFIER", "Simulation"], "entity" : ["IDENTIFIER", "STD_07100_bad"], "ARCHITECTURE_DECLARATIVE_PART" : [{ |
10 |
"declaration" : ["SIGNAL_DECLARATION", { |
11 |
"names" : [["IDENTIFIER", "Clock"]], "typ" : { |
12 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
13 |
, "init_val" : ["EXPRESSION", { |
14 |
"args" : [["EXPRESSION", { |
15 |
"args" : [["EXPRESSION", { |
16 |
"args" : [["EXPRESSION", { |
17 |
"args" : [["CONSTANT_VALUE", { |
18 |
"value" : ["CST_LITERAL", "'0'"]} |
19 |
]]} |
20 |
]]} |
21 |
]]} |
22 |
]]} |
23 |
]} |
24 |
]} |
25 |
, { |
26 |
"declaration" : ["SIGNAL_DECLARATION", { |
27 |
"names" : [["IDENTIFIER", "Reset_n"]], "typ" : { |
28 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
29 |
} |
30 |
]} |
31 |
, { |
32 |
"declaration" : ["SIGNAL_DECLARATION", { |
33 |
"names" : [["IDENTIFIER", "D_Signal"]], "typ" : { |
34 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
35 |
} |
36 |
]} |
37 |
, { |
38 |
"declaration" : ["SIGNAL_DECLARATION", { |
39 |
"names" : [["IDENTIFIER", "Q_Signal"]], "typ" : { |
40 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
41 |
} |
42 |
]} |
43 |
, { |
44 |
"declaration" : ["COMPONENT_DECLARATION", { |
45 |
"name" : ["IDENTIFIER", "DFlipFlop"], "ports" : [{ |
46 |
"names" : [["IDENTIFIER", "i_Clock"]], "mode" : ["in"], "typ" : { |
47 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
48 |
} |
49 |
, { |
50 |
"names" : [["IDENTIFIER", "i_Reset_n"]], "mode" : ["in"], "typ" : { |
51 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
52 |
} |
53 |
, { |
54 |
"names" : [["IDENTIFIER", "i_D"]], "mode" : ["in"], "typ" : { |
55 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
56 |
} |
57 |
, { |
58 |
"names" : [["IDENTIFIER", "o_Q"]], "mode" : ["out"], "typ" : { |
59 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
60 |
} |
61 |
, { |
62 |
"names" : [["IDENTIFIER", "o_Q_n"]], "mode" : ["out"], "typ" : { |
63 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
64 |
} |
65 |
]} |
66 |
]} |
67 |
], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", { |
68 |
"name" : ["IDENTIFIER", "T_DFlipFlop"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{ |
69 |
"formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "Clock"]} |
70 |
, { |
71 |
"formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "Reset_n"]} |
72 |
, { |
73 |
"formal_name" : ["SIMPLE_NAME", "i_D"], "actual_designator" : ["SIMPLE_NAME", "D_Signal"]} |
74 |
, { |
75 |
"formal_name" : ["SIMPLE_NAME", "o_Q"], "actual_designator" : ["SIMPLE_NAME", "Q_Signal"]} |
76 |
, { |
77 |
"formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["OPEN"]} |
78 |
]} |
79 |
], ["PROCESS_STATEMENT", {
|
80 |
"id" : ["IDENTIFIER", "P_Clock"], "PROCESS_STATEMENT_PART" : [["SIGNAL_ASSIGNMENT_STATEMENT", { |
81 |
"lhs" : ["SIMPLE_NAME", "Clock"], "rhs" : [{ |
82 |
"value" : ["EXPRESSION", { |
83 |
"args" : [["EXPRESSION", { |
84 |
"args" : [["EXPRESSION", { |
85 |
"args" : [["EXPRESSION", { |
86 |
"id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "Clock"]]]} |
87 |
]]} |
88 |
]]} |
89 |
]]} |
90 |
], "delay" : ["EXPRESSION", { |
91 |
"args" : [["EXPRESSION", { |
92 |
"args" : [["EXPRESSION", { |
93 |
"args" : [["EXPRESSION", { |
94 |
"args" : [["CONSTANT_VALUE", { |
95 |
"value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]} |
96 |
]]} |
97 |
]]} |
98 |
]]} |
99 |
]]} |
100 |
]} |
101 |
]} |
102 |
]]} |
103 |
], ["PROCESS_STATEMENT", {
|
104 |
"id" : ["IDENTIFIER", "P_Test"], "PROCESS_STATEMENT_PART" : [["SIGNAL_ASSIGNMENT_STATEMENT", { |
105 |
"lhs" : ["SIMPLE_NAME", "Reset_n"], "rhs" : [{ |
106 |
"value" : ["EXPRESSION", { |
107 |
"args" : [["EXPRESSION", { |
108 |
"args" : [["EXPRESSION", { |
109 |
"args" : [["EXPRESSION", { |
110 |
"args" : [["CONSTANT_VALUE", { |
111 |
"value" : ["CST_LITERAL", "'0'"]} |
112 |
]]} |
113 |
]]} |
114 |
]]} |
115 |
]]} |
116 |
]} |
117 |
]} |
118 |
], ["SIGNAL_ASSIGNMENT_STATEMENT", {
|
119 |
"lhs" : ["SIMPLE_NAME", "D_Signal"], "rhs" : [{ |
120 |
"value" : ["EXPRESSION", { |
121 |
"args" : [["EXPRESSION", { |
122 |
"args" : [["EXPRESSION", { |
123 |
"args" : [["EXPRESSION", { |
124 |
"args" : [["CONSTANT_VALUE", { |
125 |
"value" : ["CST_LITERAL", "'0'"]} |
126 |
]]} |
127 |
]]} |
128 |
]]} |
129 |
]]} |
130 |
]} |
131 |
]} |
132 |
], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", { |
133 |
"lhs" : ["SIMPLE_NAME", "Reset_n"], "rhs" : [{ |
134 |
"value" : ["EXPRESSION", { |
135 |
"args" : [["EXPRESSION", { |
136 |
"args" : [["EXPRESSION", { |
137 |
"args" : [["EXPRESSION", { |
138 |
"args" : [["CONSTANT_VALUE", { |
139 |
"value" : ["CST_LITERAL", "'1'"]} |
140 |
]]} |
141 |
]]} |
142 |
]]} |
143 |
]]} |
144 |
]} |
145 |
]} |
146 |
], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", { |
147 |
"lhs" : ["SIMPLE_NAME", "D_Signal"], "rhs" : [{ |
148 |
"value" : ["EXPRESSION", { |
149 |
"args" : [["EXPRESSION", { |
150 |
"args" : [["EXPRESSION", { |
151 |
"args" : [["EXPRESSION", { |
152 |
"args" : [["CONSTANT_VALUE", { |
153 |
"value" : ["CST_LITERAL", "'1'"]} |
154 |
]]} |
155 |
]]} |
156 |
]]} |
157 |
]]} |
158 |
]} |
159 |
]} |
160 |
], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", { |
161 |
"lhs" : ["SIMPLE_NAME", "D_Signal"], "rhs" : [{ |
162 |
"value" : ["EXPRESSION", { |
163 |
"args" : [["EXPRESSION", { |
164 |
"args" : [["EXPRESSION", { |
165 |
"args" : [["EXPRESSION", { |
166 |
"args" : [["CONSTANT_VALUE", { |
167 |
"value" : ["CST_LITERAL", "'0'"]} |
168 |
]]} |
169 |
]]} |
170 |
]]} |
171 |
]]} |
172 |
]} |
173 |
]} |
174 |
], ["WAIT_STATEMENT"]]}
|
175 |
]]} |
176 |
]} |
177 |
]} |
178 |
} |