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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / STD_07100_bad.json @ 3fd18385

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "IEEE"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "IEEE"], ["SIMPLE_NAME", "std_logic_1164"]]]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "IEEE"], ["SIMPLE_NAME", "numeric_std"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "STD_07100_bad"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "Simulation"], "entity" : ["IDENTIFIER", "STD_07100_bad"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "Clock"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            , "init_val" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "'0'"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "Reset_n"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "D_Signal"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "Q_Signal"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        , {
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "DFlipFlop"], "ports" : [{
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              "names" : [["IDENTIFIER", "i_Clock"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "i_Reset_n"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "i_D"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "o_Q"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "o_Q_n"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            ]}
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "T_DFlipFlop"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "Clock"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "Reset_n"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "i_D"], "actual_designator" : ["SIMPLE_NAME", "D_Signal"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "o_Q"], "actual_designator" : ["SIMPLE_NAME", "Q_Signal"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["OPEN"]}
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          ]}
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        ], ["PROCESS_STATEMENT", {
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          "id" : ["IDENTIFIER", "P_Clock"], "PROCESS_STATEMENT_PART" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "Clock"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "Clock"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "delay" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "5"], "unit_name" : ["SIMPLE_NAME", "ns"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ]]}
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        ], ["PROCESS_STATEMENT", {
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          "id" : ["IDENTIFIER", "P_Test"], "PROCESS_STATEMENT_PART" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "Reset_n"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'0'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "D_Signal"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'0'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "Reset_n"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'1'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "D_Signal"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'1'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"], ["SIGNAL_ASSIGNMENT_STATEMENT", {
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            "lhs" : ["SIMPLE_NAME", "D_Signal"], "rhs" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'0'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ], ["WAIT_STATEMENT"]]}
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        ]]}
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      ]}
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    ]}
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  }