lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / STD_03600_bad.json @ 3fd18385
History | View | Annotate | Download (11.7 KB)
| 1 |
{
|
|---|---|
| 2 |
"DESIGN_FILE" : {
|
| 3 |
"design_units" : [{
|
| 4 |
"contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "IEEE"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "IEEE"], ["SIMPLE_NAME", "std_logic_1164"]]]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "IEEE"], ["SIMPLE_NAME", "numeric_std"]]]]]], "library" : ["ENTITY_DECLARATION", { |
| 5 |
"name" : ["IDENTIFIER", "STD_03600_bad"], "ports" : [{ |
| 6 |
"names" : [["IDENTIFIER", "i_Reset_n"]], "mode" : ["in"], "typ" : { |
| 7 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
| 8 |
} |
| 9 |
, {
|
| 10 |
"names" : [["IDENTIFIER", "i_Clock"]], "mode" : ["in"], "typ" : { |
| 11 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
| 12 |
} |
| 13 |
, {
|
| 14 |
"names" : [["IDENTIFIER", "i_D"]], "mode" : ["in"], "typ" : { |
| 15 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
| 16 |
} |
| 17 |
, {
|
| 18 |
"names" : [["IDENTIFIER", "o_Q"]], "mode" : ["out"], "typ" : { |
| 19 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
| 20 |
} |
| 21 |
], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []} |
| 22 |
]} |
| 23 |
, {
|
| 24 |
"contexts" : [], "library" : ["ARCHITECTURE_BODY", { |
| 25 |
"name" : ["IDENTIFIER", "Behavioral"], "entity" : ["IDENTIFIER", "STD_03600_bad"], "ARCHITECTURE_DECLARATIVE_PART" : [{ |
| 26 |
"declaration" : ["SIGNAL_DECLARATION", { |
| 27 |
"names" : [["IDENTIFIER", "D_r1"]], "typ" : { |
| 28 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
| 29 |
} |
| 30 |
]} |
| 31 |
, {
|
| 32 |
"declaration" : ["SIGNAL_DECLARATION", { |
| 33 |
"names" : [["IDENTIFIER", "D_r2"]], "typ" : { |
| 34 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
| 35 |
} |
| 36 |
]} |
| 37 |
, {
|
| 38 |
"declaration" : ["SIGNAL_DECLARATION", { |
| 39 |
"names" : [["IDENTIFIER", "D_re"]], "typ" : { |
| 40 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
| 41 |
} |
| 42 |
]} |
| 43 |
, {
|
| 44 |
"declaration" : ["SIGNAL_DECLARATION", { |
| 45 |
"names" : [["IDENTIFIER", "Reset"]], "typ" : { |
| 46 |
"name" : ["SIMPLE_NAME", "std_logic"]} |
| 47 |
} |
| 48 |
]} |
| 49 |
], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", { |
| 50 |
"id" : ["IDENTIFIER", "P_First_Register"], "active_sigs" : [["SIMPLE_NAME", "i_Reset_n"], ["SIMPLE_NAME", "i_Clock"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", { |
| 51 |
"if_cases" : [{
|
| 52 |
"if_cond" : ["EXPRESSION", { |
| 53 |
"args" : [["EXPRESSION", { |
| 54 |
"args" : [["EXPRESSION", { |
| 55 |
"args" : [["EXPRESSION", { |
| 56 |
"args" : [["EXPRESSION", { |
| 57 |
"id" : "=", "args" : [["EXPRESSION", { |
| 58 |
"args" : [["EXPRESSION", { |
| 59 |
"args" : [["EXPRESSION", { |
| 60 |
"args" : [["CALL", ["SIMPLE_NAME", "i_Reset_n"]]]} |
| 61 |
]]} |
| 62 |
]]} |
| 63 |
], ["EXPRESSION", {
|
| 64 |
"args" : [["EXPRESSION", { |
| 65 |
"args" : [["EXPRESSION", { |
| 66 |
"args" : [["CONSTANT_VALUE", { |
| 67 |
"value" : ["CST_LITERAL", "'0'"]} |
| 68 |
]]} |
| 69 |
]]} |
| 70 |
]]} |
| 71 |
]]} |
| 72 |
]]} |
| 73 |
]]} |
| 74 |
]]} |
| 75 |
]]} |
| 76 |
], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", { |
| 77 |
"lhs" : ["SIMPLE_NAME", "D_r1"], "rhs" : [{ |
| 78 |
"value" : ["EXPRESSION", { |
| 79 |
"args" : [["EXPRESSION", { |
| 80 |
"args" : [["EXPRESSION", { |
| 81 |
"args" : [["EXPRESSION", { |
| 82 |
"args" : [["CONSTANT_VALUE", { |
| 83 |
"value" : ["CST_LITERAL", "'0'"]} |
| 84 |
]]} |
| 85 |
]]} |
| 86 |
]]} |
| 87 |
]]} |
| 88 |
]} |
| 89 |
]} |
| 90 |
]]} |
| 91 |
, {
|
| 92 |
"if_cond" : ["EXPRESSION", { |
| 93 |
"args" : [["EXPRESSION", { |
| 94 |
"args" : [["EXPRESSION", { |
| 95 |
"args" : [["EXPRESSION", { |
| 96 |
"args" : [["EXPRESSION", { |
| 97 |
"args" : [["EXPRESSION", { |
| 98 |
"args" : [["EXPRESSION", { |
| 99 |
"args" : [["EXPRESSION", { |
| 100 |
"args" : [["CALL", ["INDEXED_NAME", { |
| 101 |
"id" : ["SIMPLE_NAME", "rising_edge"], "exprs" : [["EXPRESSION", { |
| 102 |
"args" : [["EXPRESSION", { |
| 103 |
"args" : [["EXPRESSION", { |
| 104 |
"args" : [["EXPRESSION", { |
| 105 |
"args" : [["CALL", ["SIMPLE_NAME", "i_Clock"]]]} |
| 106 |
]]} |
| 107 |
]]} |
| 108 |
]]} |
| 109 |
]]} |
| 110 |
]]]} |
| 111 |
]]} |
| 112 |
]]} |
| 113 |
]]} |
| 114 |
]]} |
| 115 |
]]} |
| 116 |
]]} |
| 117 |
]]} |
| 118 |
], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", { |
| 119 |
"lhs" : ["SIMPLE_NAME", "D_r1"], "rhs" : [{ |
| 120 |
"value" : ["EXPRESSION", { |
| 121 |
"args" : [["EXPRESSION", { |
| 122 |
"args" : [["EXPRESSION", { |
| 123 |
"args" : [["EXPRESSION", { |
| 124 |
"args" : [["CALL", ["SIMPLE_NAME", "i_D"]]]} |
| 125 |
]]} |
| 126 |
]]} |
| 127 |
]]} |
| 128 |
]} |
| 129 |
]} |
| 130 |
]]} |
| 131 |
]} |
| 132 |
]]} |
| 133 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
| 134 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "Reset"], "rhs" : [{ |
| 135 |
"expr" : [{
|
| 136 |
"value" : ["EXPRESSION", { |
| 137 |
"args" : [["EXPRESSION", { |
| 138 |
"args" : [["EXPRESSION", { |
| 139 |
"args" : [["EXPRESSION", { |
| 140 |
"id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "i_Reset_n"]]]} |
| 141 |
]]} |
| 142 |
]]} |
| 143 |
]]} |
| 144 |
]} |
| 145 |
]} |
| 146 |
]} |
| 147 |
], ["PROCESS_STATEMENT", {
|
| 148 |
"id" : ["IDENTIFIER", "P_Second_Register"], "active_sigs" : [["SIMPLE_NAME", "Reset"], ["SIMPLE_NAME", "i_Clock"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", { |
| 149 |
"if_cases" : [{
|
| 150 |
"if_cond" : ["EXPRESSION", { |
| 151 |
"args" : [["EXPRESSION", { |
| 152 |
"args" : [["EXPRESSION", { |
| 153 |
"args" : [["EXPRESSION", { |
| 154 |
"args" : [["EXPRESSION", { |
| 155 |
"id" : "=", "args" : [["EXPRESSION", { |
| 156 |
"args" : [["EXPRESSION", { |
| 157 |
"args" : [["EXPRESSION", { |
| 158 |
"args" : [["CALL", ["SIMPLE_NAME", "Reset"]]]} |
| 159 |
]]} |
| 160 |
]]} |
| 161 |
], ["EXPRESSION", {
|
| 162 |
"args" : [["EXPRESSION", { |
| 163 |
"args" : [["EXPRESSION", { |
| 164 |
"args" : [["CONSTANT_VALUE", { |
| 165 |
"value" : ["CST_LITERAL", "'1'"]} |
| 166 |
]]} |
| 167 |
]]} |
| 168 |
]]} |
| 169 |
]]} |
| 170 |
]]} |
| 171 |
]]} |
| 172 |
]]} |
| 173 |
]]} |
| 174 |
], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", { |
| 175 |
"lhs" : ["SIMPLE_NAME", "D_r2"], "rhs" : [{ |
| 176 |
"value" : ["EXPRESSION", { |
| 177 |
"args" : [["EXPRESSION", { |
| 178 |
"args" : [["EXPRESSION", { |
| 179 |
"args" : [["EXPRESSION", { |
| 180 |
"args" : [["CONSTANT_VALUE", { |
| 181 |
"value" : ["CST_LITERAL", "'0'"]} |
| 182 |
]]} |
| 183 |
]]} |
| 184 |
]]} |
| 185 |
]]} |
| 186 |
]} |
| 187 |
]} |
| 188 |
], ["SIGNAL_ASSIGNMENT_STATEMENT", {
|
| 189 |
"lhs" : ["SIMPLE_NAME", "D_re"], "rhs" : [{ |
| 190 |
"value" : ["EXPRESSION", { |
| 191 |
"args" : [["EXPRESSION", { |
| 192 |
"args" : [["EXPRESSION", { |
| 193 |
"args" : [["EXPRESSION", { |
| 194 |
"args" : [["CONSTANT_VALUE", { |
| 195 |
"value" : ["CST_LITERAL", "'0'"]} |
| 196 |
]]} |
| 197 |
]]} |
| 198 |
]]} |
| 199 |
]]} |
| 200 |
]} |
| 201 |
]} |
| 202 |
]]} |
| 203 |
, {
|
| 204 |
"if_cond" : ["EXPRESSION", { |
| 205 |
"args" : [["EXPRESSION", { |
| 206 |
"args" : [["EXPRESSION", { |
| 207 |
"args" : [["EXPRESSION", { |
| 208 |
"args" : [["EXPRESSION", { |
| 209 |
"args" : [["EXPRESSION", { |
| 210 |
"args" : [["EXPRESSION", { |
| 211 |
"args" : [["EXPRESSION", { |
| 212 |
"args" : [["CALL", ["INDEXED_NAME", { |
| 213 |
"id" : ["SIMPLE_NAME", "rising_edge"], "exprs" : [["EXPRESSION", { |
| 214 |
"args" : [["EXPRESSION", { |
| 215 |
"args" : [["EXPRESSION", { |
| 216 |
"args" : [["EXPRESSION", { |
| 217 |
"args" : [["CALL", ["SIMPLE_NAME", "i_Clock"]]]} |
| 218 |
]]} |
| 219 |
]]} |
| 220 |
]]} |
| 221 |
]]} |
| 222 |
]]]} |
| 223 |
]]} |
| 224 |
]]} |
| 225 |
]]} |
| 226 |
]]} |
| 227 |
]]} |
| 228 |
]]} |
| 229 |
]]} |
| 230 |
], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", { |
| 231 |
"lhs" : ["SIMPLE_NAME", "D_r2"], "rhs" : [{ |
| 232 |
"value" : ["EXPRESSION", { |
| 233 |
"args" : [["EXPRESSION", { |
| 234 |
"args" : [["EXPRESSION", { |
| 235 |
"args" : [["EXPRESSION", { |
| 236 |
"args" : [["CALL", ["SIMPLE_NAME", "D_r1"]]]} |
| 237 |
]]} |
| 238 |
]]} |
| 239 |
]]} |
| 240 |
]} |
| 241 |
]} |
| 242 |
], ["SIGNAL_ASSIGNMENT_STATEMENT", {
|
| 243 |
"lhs" : ["SIMPLE_NAME", "D_re"], "rhs" : [{ |
| 244 |
"value" : ["EXPRESSION", { |
| 245 |
"id" : "and", "args" : [["EXPRESSION", { |
| 246 |
"args" : [["EXPRESSION", { |
| 247 |
"args" : [["EXPRESSION", { |
| 248 |
"args" : [["EXPRESSION", { |
| 249 |
"args" : [["CALL", ["SIMPLE_NAME", "D_r1"]]]} |
| 250 |
]]} |
| 251 |
]]} |
| 252 |
]]} |
| 253 |
], ["EXPRESSION", {
|
| 254 |
"args" : [["EXPRESSION", { |
| 255 |
"args" : [["EXPRESSION", { |
| 256 |
"args" : [["EXPRESSION", { |
| 257 |
"id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "D_r2"]]]} |
| 258 |
]]} |
| 259 |
]]} |
| 260 |
]]} |
| 261 |
]]} |
| 262 |
]} |
| 263 |
]} |
| 264 |
]]} |
| 265 |
]} |
| 266 |
]]} |
| 267 |
], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
|
| 268 |
"postponed" : false, "lhs" : ["SIMPLE_NAME", "o_Q"], "rhs" : [{ |
| 269 |
"expr" : [{
|
| 270 |
"value" : ["EXPRESSION", { |
| 271 |
"args" : [["EXPRESSION", { |
| 272 |
"args" : [["EXPRESSION", { |
| 273 |
"args" : [["EXPRESSION", { |
| 274 |
"args" : [["CALL", ["SIMPLE_NAME", "D_re"]]]} |
| 275 |
]]} |
| 276 |
]]} |
| 277 |
]]} |
| 278 |
]} |
| 279 |
]} |
| 280 |
]} |
| 281 |
]]} |
| 282 |
]} |
| 283 |
]} |
| 284 |
} |