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Revision 3fd18385 vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_04.json

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vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_04.json
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              ]]}
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            ]}
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          ], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["INDEXED_NAME", {
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              "id" : ["SIMPLE_NAME", "std_ulogic_vector"], "exprs" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CALL", ["FUNCTION_CALL", {
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                      "id" : ["SIMPLE_NAME", "std_ulogic_vector"], "assoc_list" : [{
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                        "actual_designator" : ["SIMPLE_NAME", "destination"]}
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                      ]}
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                    ]]]}
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "destination"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
......
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              ]]}
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            ], "actual_designator" : ["SIMPLE_NAME", "source1"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "constant_ROM"], "inst_unit" : ["SIMPLE_NAME", "ROM"], "inst_unit_type" : "component", "port_map" : [{
......
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              ]]}
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            ], "actual_designator" : ["SIMPLE_NAME", "source2"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ]]}
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      ]}

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