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Revision 3fd18385 vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_17.json

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vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_17.json
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          , {
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            "formal_name" : ["SIMPLE_NAME", "a_d"], "actual_designator" : ["SIMPLE_NAME", "cpu_a_d"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "main_memory"], "inst_unit" : ["SIMPLE_NAME", "memory"], "inst_unit_type" : "component", "port_map" : [{
......
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              ]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "serial_interface_a"], "inst_unit" : ["SIMPLE_NAME", "serial_interface"], "inst_unit_type" : "component", "port_map" : [{
......
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              ]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ]]}
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      ]}

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