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Revision 3fd18385 vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_09.json

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vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_09.json
54 54
          "name" : ["IDENTIFIER", "bus_module_1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "bus_module"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "behavioral"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "synch"], "actual_designator" : ["SIMPLE_NAME", "synch_control"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bus_module_2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "bus_module"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "behavioral"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "synch"], "actual_designator" : ["SIMPLE_NAME", "synch_control"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["OPEN"]}
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          ]}
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        ]]}
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      ]}

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