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Revision 3fd18385 vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_04500_bad.json

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vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_04500_bad.json
112 112
          , {
113 113
            "formal_name" : ["SIMPLE_NAME", "o_Q"], "actual_designator" : ["SIMPLE_NAME", "QA"]}
114 114
          , {
115
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
115
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["OPEN"]}
116 116
          ]}
117 117
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
118 118
          "name" : ["IDENTIFIER", "DFF2"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
......
124 124
          , {
125 125
            "formal_name" : ["SIMPLE_NAME", "o_Q"], "actual_designator" : ["SIMPLE_NAME", "QB"]}
126 126
          , {
127
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
127
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["OPEN"]}
128 128
          ]}
129 129
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
130 130
          "name" : ["IDENTIFIER", "DFF3"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
......
136 136
          , {
137 137
            "formal_name" : ["SIMPLE_NAME", "o_Q"], "actual_designator" : ["SIMPLE_NAME", "o_QC"]}
138 138
          , {
139
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
139
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["OPEN"]}
140 140
          ]}
141 141
        ], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
142 142
          "postponed" : false, "lhs" : ["SIMPLE_NAME", "o_QA"], "rhs" : [{

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