lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc1757.vhd @ 3fd18385
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| 1 | 3fd18385 | Arnaud Dieumegard | |
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| 2 | -- Copyright (C) 2001 Bill Billowitch. |
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| 3 | |||
| 4 | -- Some of the work to develop this test suite was done with Air Force |
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| 5 | -- support. The Air Force and Bill Billowitch assume no |
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| 6 | -- responsibilities for this software. |
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| 7 | |||
| 8 | -- This file is part of VESTs (Vhdl tESTs). |
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| 9 | |||
| 10 | -- VESTs is free software; you can redistribute it and/or modify it |
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| 11 | -- under the terms of the GNU General Public License as published by the |
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| 12 | -- Free Software Foundation; either version 2 of the License, or (at |
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| 13 | -- your option) any later version. |
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| 14 | |||
| 15 | -- VESTs is distributed in the hope that it will be useful, but WITHOUT |
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| 16 | -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 17 | -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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| 18 | -- for more details. |
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| 19 | |||
| 20 | -- You should have received a copy of the GNU General Public License |
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| 21 | -- along with VESTs; if not, write to the Free Software Foundation, |
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| 22 | -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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| 23 | |||
| 24 | -- --------------------------------------------------------------------- |
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| 25 | -- |
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| 26 | -- $Id: tc1757.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $ |
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| 27 | -- $Revision: 1.2 $ |
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| 28 | -- |
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| 29 | -- --------------------------------------------------------------------- |
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| 30 | |||
| 31 | ENTITY c09s05b01x00p01n01i01757ent IS |
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| 32 | END c09s05b01x00p01n01i01757ent; |
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| 33 | |||
| 34 | ARCHITECTURE c09s05b01x00p01n01i01757arch OF c09s05b01x00p01n01i01757ent IS |
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| 35 | type t_wlogic is (U, D, Z0, Z1, ZDX, DZX, ZX); |
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| 36 | signal count : integer ; |
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| 37 | signal ECLK : t_wlogic; |
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| 38 | signal ECLK2 : t_wlogic; |
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| 39 | signal ECL : integer := 1; |
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| 40 | BEGIN |
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| 41 | count <= 0 after 0 ns, |
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| 42 | 1 after 10 ns, |
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| 43 | 2 after 20 ns, |
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| 44 | 3 after 30 ns, |
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| 45 | 4 after 40 ns, |
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| 46 | 5 after 50 ns, |
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| 47 | 6 after 60 ns; |
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| 48 | ---------------------------------------------------------------------- |
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| 49 | ECLK <= transport |
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| 50 | U after 1 ns WHEN count=0 ELSE |
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| 51 | D after 1 ns WHEN count=1 ELSE |
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| 52 | Z0 after 1 ns WHEN count=2 ELSE |
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| 53 | Z1 after 1 ns WHEN count=3 ELSE |
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| 54 | ZDX after 1 ns WHEN count=4 ELSE |
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| 55 | DZX after 1 ns WHEN count=5 ELSE |
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| 56 | ZX after 1 ns ; |
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| 57 | TESTING: PROCESS(count) |
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| 58 | BEGIN |
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| 59 | if count = 0 then |
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| 60 | ECLK2 <= transport U after 1 ns; |
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| 61 | elsif count = 1 then |
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| 62 | ECLK2 <= transport D after 1 ns; |
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| 63 | elsif count = 2 then |
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| 64 | ECLK2 <= transport Z0 after 1 ns; |
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| 65 | elsif count = 3 then |
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| 66 | ECLK2 <= transport Z1 after 1 ns; |
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| 67 | elsif count = 4 then |
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| 68 | ECLK2 <= transport ZDX after 1 ns; |
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| 69 | elsif count = 5 then |
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| 70 | ECLK2 <= transport DZX after 1 ns; |
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| 71 | else |
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| 72 | ECLK2 <= transport ZX after 1 ns; |
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| 73 | end if; |
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| 74 | END PROCESS TESTING; |
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| 75 | PROCESS(ECLK,ECLK2) |
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| 76 | BEGIN |
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| 77 | if now = 0 ns then |
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| 78 | NULL; |
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| 79 | elsif (now = 1 ns) and (ECLK /= ECLK2) then |
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| 80 | assert FALSE |
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| 81 | report "FAILED TEST" |
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| 82 | severity ERROR; |
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| 83 | ECL <= 0; |
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| 84 | elsif (now = 11 ns) and (ECLK /= ECLK2) then |
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| 85 | assert FALSE |
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| 86 | report "FAILED TEST" |
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| 87 | severity ERROR; |
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| 88 | ECL <= 0; |
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| 89 | elsif (now = 21 ns) and (ECLK /= ECLK2) then |
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| 90 | assert FALSE |
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| 91 | report "FAILED TEST" |
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| 92 | severity ERROR; |
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| 93 | ECL <= 0; |
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| 94 | elsif (now = 31 ns) and (ECLK /= ECLK2) then |
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| 95 | assert FALSE |
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| 96 | report "FAILED TEST" |
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| 97 | severity ERROR; |
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| 98 | ECL <= 0; |
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| 99 | elsif (now = 41 ns) and (ECLK /= ECLK2) then |
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| 100 | assert FALSE |
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| 101 | report "FAILED TEST" |
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| 102 | severity ERROR; |
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| 103 | ECL <= 0; |
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| 104 | elsif (now = 51 ns) and (ECLK /= ECLK2) then |
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| 105 | assert FALSE |
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| 106 | report "FAILED TEST" |
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| 107 | severity ERROR; |
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| 108 | ECL <= 0; |
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| 109 | elsif (now = 61 ns) and (ECLK /= ECLK2) then |
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| 110 | assert FALSE |
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| 111 | report "FAILED TEST" |
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| 112 | severity ERROR; |
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| 113 | ECL <= 0; |
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| 114 | end if; |
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| 115 | END PROCESS; |
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| 116 | PROCESS(ECLK,ECLK2) |
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| 117 | BEGIN |
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| 118 | if (now > 60 ns) and (ECL = 1) then |
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| 119 | assert FALSE |
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| 120 | report "***PASSED TEST: c09s05b01x00p01n01i01757" |
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| 121 | severity NOTE; |
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| 122 | elsif (now > 60 ns) and (ECL = 0) then |
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| 123 | assert FALSE |
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| 124 | report "***FAILED TEST: c09s05b01x00p01n01i01757 - The conditional signal assignment represents a process statement in which the signal transform is an if statement." |
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| 125 | severity ERROR; |
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| 126 | end if; |
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| 127 | END PROCESS; |
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| 128 | |||
| 129 | END c09s05b01x00p01n01i01757arch; |