lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / billowitch / compliant / tc1079.vhd @ 3fd18385
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1 | 3fd18385 | Arnaud Dieumegard | |
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2 | -- Copyright (C) 2001 Bill Billowitch. |
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3 | |||
4 | -- Some of the work to develop this test suite was done with Air Force |
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5 | -- support. The Air Force and Bill Billowitch assume no |
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6 | -- responsibilities for this software. |
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7 | |||
8 | -- This file is part of VESTs (Vhdl tESTs). |
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9 | |||
10 | -- VESTs is free software; you can redistribute it and/or modify it |
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11 | -- under the terms of the GNU General Public License as published by the |
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12 | -- Free Software Foundation; either version 2 of the License, or (at |
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13 | -- your option) any later version. |
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14 | |||
15 | -- VESTs is distributed in the hope that it will be useful, but WITHOUT |
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16 | -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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17 | -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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18 | -- for more details. |
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19 | |||
20 | -- You should have received a copy of the GNU General Public License |
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21 | -- along with VESTs; if not, write to the Free Software Foundation, |
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22 | -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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23 | |||
24 | -- --------------------------------------------------------------------- |
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25 | -- |
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26 | -- $Id: tc1079.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $ |
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27 | -- $Revision: 1.2 $ |
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28 | -- |
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29 | -- --------------------------------------------------------------------- |
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30 | |||
31 | ENTITY c06s05b00x00p01n02i01079ent IS |
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32 | END c06s05b00x00p01n02i01079ent; |
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33 | |||
34 | ARCHITECTURE c06s05b00x00p01n02i01079arch OF c06s05b00x00p01n02i01079ent IS |
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35 | SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 ); |
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36 | SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 ); |
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37 | |||
38 | SIGNAL v_slice : bit_vector_8 := B"1010_1100"; |
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39 | |||
40 | procedure subprogram ( signal v : out bit_vector_4 ) is |
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41 | begin |
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42 | v <= B"0101" after 10 ns; |
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43 | end ; |
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44 | |||
45 | BEGIN |
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46 | TESTING: PROCESS |
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47 | BEGIN |
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48 | subprogram ( v_slice ( 0 to 3 ) ); |
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49 | wait for 11 ns; |
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50 | assert NOT(v_slice = B"0101_1100") |
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51 | report "***PASSED TEST: c06s05b00x00p01n02i01079" |
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52 | severity NOTE; |
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53 | assert (v_slice = B"0101_1100") |
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54 | report "***FAILED TEST: c06s05b00x00p01n02i01079 - A slice of a signal should still be a signal." |
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55 | severity ERROR; |
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56 | wait; |
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57 | END PROCESS TESTING; |
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58 | |||
59 | END c06s05b00x00p01n02i01079arch; |