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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_15_dlxtst-b.json @ 3fd18385

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1 2051e520 Arnaud Dieumegard 
{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "bench"], "entity" : ["IDENTIFIER", "dlx_test"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "use_clause" : ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "dlx_types"]]]]]}
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        , {
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "clock_gen"], "ports" : [{
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              "names" : [["IDENTIFIER", "phi1"], ["IDENTIFIER", "phi2"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "reset"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            ]}
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          ]}
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        , {
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "memory"], "ports" : [{
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              "names" : [["IDENTIFIER", "phi1"], ["IDENTIFIER", "phi2"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "a"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "dlx_address"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "d"]], "mode" : ["inout"], "typ" : {
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                "name" : ["SIMPLE_NAME", "dlx_word"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "width"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "dlx_mem_width"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "write_enable"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "burst"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              , "expr" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'0'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            , {
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              "names" : [["IDENTIFIER", "mem_enable"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "ready"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            ]}
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          ]}
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        , {
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "dlx"], "ports" : [{
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              "names" : [["IDENTIFIER", "phi1"], ["IDENTIFIER", "phi2"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "reset"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "halt"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "a"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "dlx_address"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "d"]], "mode" : ["inout"], "typ" : {
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                "name" : ["SIMPLE_NAME", "dlx_word"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "width"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "dlx_mem_width"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "write_enable"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "ifetch"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "mem_enable"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "ready"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            ]}
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "phi1"], ["IDENTIFIER", "phi2"], ["IDENTIFIER", "reset"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "a"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "dlx_address"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "d"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "dlx_word"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "halt"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "width"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "dlx_mem_width"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "write_enable"], ["IDENTIFIER", "mem_enable"], ["IDENTIFIER", "ifetch"], ["IDENTIFIER", "ready"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "cg"], "inst_unit" : ["SIMPLE_NAME", "clock_gen"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "phi1"], "actual_designator" : ["SIMPLE_NAME", "phi1"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "phi2"], "actual_designator" : ["SIMPLE_NAME", "phi2"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "reset"], "actual_designator" : ["SIMPLE_NAME", "reset"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "mem"], "inst_unit" : ["SIMPLE_NAME", "memory"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "phi1"], "actual_designator" : ["SIMPLE_NAME", "phi1"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "phi2"], "actual_designator" : ["SIMPLE_NAME", "phi2"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "a"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "d"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "width"], "actual_designator" : ["SIMPLE_NAME", "width"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "write_enable"], "actual_designator" : ["SIMPLE_NAME", "write_enable"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "burst"], "actual_designator" : ["OPEN"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "mem_enable"], "actual_designator" : ["SIMPLE_NAME", "mem_enable"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "ready"], "actual_designator" : ["SIMPLE_NAME", "ready"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "proc"], "inst_unit" : ["SIMPLE_NAME", "dlx"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "phi1"], "actual_designator" : ["SIMPLE_NAME", "phi1"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "phi2"], "actual_designator" : ["SIMPLE_NAME", "phi2"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "reset"], "actual_designator" : ["SIMPLE_NAME", "reset"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "halt"], "actual_designator" : ["SIMPLE_NAME", "halt"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "a"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "d"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "width"], "actual_designator" : ["SIMPLE_NAME", "width"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "write_enable"], "actual_designator" : ["SIMPLE_NAME", "write_enable"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "ifetch"], "actual_designator" : ["SIMPLE_NAME", "ifetch"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "mem_enable"], "actual_designator" : ["SIMPLE_NAME", "mem_enable"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "ready"], "actual_designator" : ["SIMPLE_NAME", "ready"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }