Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_05_ch_05_22.vhd @ 3fd18385

History | View | Annotate | Download (2.42 KB)

1 3fd18385 Arnaud Dieumegard
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4
-- This file is part of VESTs (Vhdl tESTs).
5
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_05_ch_05_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26
27
-- code from book:
28
29
entity mux4 is
30
  port ( i0, i1, i2, i3, sel0, sel1 : in bit;
31
         z : out bit );
32
end entity mux4;
33
34
-- end of code from book
35
36
37
----------------------------------------------------------------
38
39
40
architecture functional of mux4 is
41
begin
42
43
  out_select : process (sel0, sel1, i0, i1, i2, i3) is
44
                                                      subtype bits_2 is bit_vector(1 downto 0);
45
  begin
46
    case bits_2'(sel1, sel0) is
47
      when "00" =>  z <= i0;
48
      when "01" =>  z <= i1;
49
      when "10" =>  z <= i2;
50
      when "11" =>  z <= i3;
51
    end case;
52
  end process out_select;
53
54
end architecture functional;
55
56
57
----------------------------------------------------------------
58
59
60
entity ch_05_22 is
61
62
end entity ch_05_22;
63
64
65
----------------------------------------------------------------
66
67
68
architecture test of ch_05_22 is
69
70
  signal select_line, line0, line1, result_line : bit;
71
72
begin
73
74
75
  -- code from book:
76
77
  a_mux : entity work.mux4
78
    port map ( sel0 => select_line, i0 => line0, i1 => line1,
79
               z => result_line,
80
               sel1 => '0', i2 => '1', i3 => '1' );
81
82
  -- end of code from book
83
84
85
  ----------------
86
87
88
  stimulus : process is
89
  begin
90
    wait for 5 ns;
91
    line0 <= '1';				wait for 5 ns;
92
    line1 <= '1';				wait for 5 ns;
93
    select_line <= '1';	wait for 5 ns;
94
    line1 <= '0';				wait for 5 ns;
95
    line0 <= '0';				wait for 5 ns;
96
97
    wait;
98
  end process stimulus;
99
100
101
end architecture test;