Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / vests / vhdl-93 / ashenden / compliant / ch_03_tb_03_10.vhd @ 3fd18385

History | View | Annotate | Download (1.73 KB)

1 3fd18385 Arnaud Dieumegard
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4
-- This file is part of VESTs (Vhdl tESTs).
5
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_03_tb_03_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26
27
entity test_bench_03_10 is
28
end entity test_bench_03_10;
29
30
architecture test_edge_triggered_register_check_timing of test_bench_03_10 is
31
32
  signal clock : bit := '0'; 
33
  signal d_in, d_out : real := 0.0;
34
35
begin
36
37
  dut : entity work.edge_triggered_register(check_timing)
38
    port map ( clock => clock, d_in => d_in, d_out => d_out );
39
40
  stumulus : process is
41
42
  begin
43
    wait for 20 ns;
44
45
    d_in <= 1.0;			wait for 10 ns;
46
    clock <= '1', '0' after 10 ns;	wait for 20 ns;
47
48
    d_in <= 2.0;			wait for 10 ns;
49
    clock <= '1', '0' after 5 ns;	wait for 20 ns;
50
51
    d_in <= 3.0;			wait for 10 ns;
52
    clock <= '1', '0' after 4 ns;	wait for 20 ns;
53
54
    wait;
55
  end process stumulus;
56
57
end architecture test_edge_triggered_register_check_timing;