lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / best-chronometer-ever / test / simple_sim.vhd @ 3fd18385
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1 | 3fd18385 | Arnaud Dieumegard | -------------------------------------------------------------------------------- |
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2 | -- SIMPLE TEST ----------------------------------------------------------------- |
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3 | -------------------------------------------------------------------------------- |
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4 | -- This test bench is meant to ensure the proper behavior of our chronometer. |
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5 | -- To avoid ridiculously long test runtimes, the Centisecond Timer should be |
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6 | -- set so it considers there are 8 clock cycles per centisecond. Similarly, |
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7 | -- the Display Manager's clock cycle target should be set to 2. |
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8 | -- The 59.99s limit should then be reached after around 959 900 ns. |
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9 | |||
10 | library IEEE; |
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11 | |||
12 | use IEEE.STD_LOGIC_1164.ALL; |
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13 | |||
14 | |||
15 | entity simple_sim is |
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16 | end simple_sim; |
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17 | |||
18 | architecture behavior of simple_sim is |
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19 | -- Constants ---------------------------------------------------------------- |
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20 | constant display_value_0: std_logic_vector(6 downto 0) := B"0000001"; |
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21 | constant display_value_1: std_logic_vector(6 downto 0) := B"1001111"; |
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22 | constant display_value_2: std_logic_vector(6 downto 0) := B"0010010"; |
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23 | constant display_value_3: std_logic_vector(6 downto 0) := B"0000110"; |
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24 | constant display_value_4: std_logic_vector(6 downto 0) := B"1001100"; |
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25 | constant display_value_5: std_logic_vector(6 downto 0) := B"0100100"; |
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26 | constant display_value_6: std_logic_vector(6 downto 0) := B"0100000"; |
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27 | constant display_value_7: std_logic_vector(6 downto 0) := B"0001111"; |
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28 | constant display_value_8: std_logic_vector(6 downto 0) := B"0000000"; |
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29 | constant display_value_9: std_logic_vector(6 downto 0) := B"0000100"; |
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30 | constant display_value_error: std_logic_vector(6 downto 0) := B"0110000"; |
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31 | |||
32 | constant miniclock_period : time := 20 ns; |
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33 | |||
34 | -- Signals ------------------------------------------------------------------ |
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35 | ---- Inputs ----------------------------------------------------------------- |
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36 | signal CK_50MHz: std_logic := '0'; |
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37 | signal reset: std_logic := '0'; |
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38 | signal BP_RAZ: std_logic := '0'; |
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39 | signal BP_START_STOP: std_logic := '0'; |
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40 | |||
41 | ---- Outputs ---------------------------------------------------------------- |
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42 | signal Display: std_logic_vector(6 downto 0); |
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43 | signal AN: std_logic_vector(3 downto 0); |
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44 | |||
45 | -- Natural representation of Display. 10 means "error". |
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46 | signal Display_N: natural range 0 to 10; |
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47 | |||
48 | -- Components --------------------------------------------------------------- |
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49 | component best_chronometer_ever is |
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50 | port |
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51 | ( |
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52 | i_clock: in std_logic; |
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53 | i_reset: in std_logic; |
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54 | i_start_bp: in std_logic; |
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55 | i_raz_bp: in std_logic; |
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56 | o_display: out std_logic_vector (6 downto 0); |
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57 | o_an: out std_logic_vector (3 downto 0) |
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58 | ); |
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59 | end component; |
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60 | |||
61 | -- Functions ---------------------------------------------------------------- |
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62 | function display_value_to_numeral (D: std_logic_vector(6 downto 0)) |
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63 | return natural is |
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64 | begin |
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65 | case D is |
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66 | when display_value_0 => return 0; |
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67 | when display_value_1 => return 1; |
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68 | when display_value_2 => return 2; |
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69 | when display_value_3 => return 3; |
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70 | when display_value_4 => return 4; |
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71 | when display_value_5 => return 5; |
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72 | when display_value_6 => return 6; |
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73 | when display_value_7 => return 7; |
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74 | when display_value_8 => return 8; |
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75 | when display_value_9 => return 9; |
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76 | when others => return 10; |
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77 | end case; |
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78 | end display_value_to_numeral; |
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79 | begin |
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80 | -- Unit Under Test ---------------------------------------------------------- |
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81 | uut: best_chronometer_ever |
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82 | port map |
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83 | ( |
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84 | i_clock => CK_50MHZ, |
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85 | i_reset => reset, |
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86 | i_start_bp => BP_START_STOP, |
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87 | i_raz_bp => BP_RAZ, |
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88 | o_display => Display, |
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89 | o_an => AN |
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90 | ); |
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91 | |||
92 | Display_N <= display_value_to_numeral(Display); |
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93 | |||
94 | -- Clock Process ------------------------------------------------------------ |
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95 | miniclock_process: process |
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96 | begin |
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97 | CK_50MHz <= '0'; |
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98 | wait for (miniclock_period / 2); |
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99 | CK_50MHz <= '1'; |
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100 | wait for (miniclock_period / 2); |
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101 | end process; |
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102 | |||
103 | -- Stimulus Process --------------------------------------------------------- |
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104 | stim_proc: process |
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105 | begin |
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106 | reset <= '1'; |
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107 | wait for 50 ns; |
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108 | reset <= '0'; |
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109 | wait for 50 ns; |
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110 | |||
111 | BP_START_STOP <= '0'; |
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112 | BP_RAZ <= '0'; |
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113 | |||
114 | wait for 100 ns; |
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115 | |||
116 | |||
117 | BP_START_STOP <= '1'; |
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118 | |||
119 | wait for 100 ns; |
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120 | |||
121 | BP_START_STOP <= '0'; |
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122 | |||
123 | wait for 10000 ns; |
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124 | |||
125 | BP_START_STOP <= '1'; |
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126 | |||
127 | wait for 100 ns; |
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128 | |||
129 | BP_START_STOP <= '0'; |
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130 | |||
131 | wait for 400 ns; |
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132 | |||
133 | BP_RAZ <= '1'; |
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134 | |||
135 | wait for 100 ns; |
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136 | |||
137 | BP_RAZ <= '0'; |
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138 | |||
139 | wait for 400 ns; |
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140 | |||
141 | BP_START_STOP <= '1'; |
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142 | |||
143 | wait for 100 ns; |
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144 | |||
145 | BP_START_STOP <= '0'; |
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146 | |||
147 | assert false report "End of Test" severity note; |
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148 | |||
149 | wait; |
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150 | |||
151 | end process; |
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152 | end; |