CristalCaveGem » LustreC » Lustrec-Tests

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-- SIMPLE TEST -----------------------------------------------------------------

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-- This test bench is meant to ensure the proper behavior of our chronometer.

-- To avoid ridiculously long test runtimes, the Centisecond Timer should be

-- set so it considers there are 8 clock cycles per centisecond. Similarly,

-- the Display Manager's clock cycle target should be set to 2.

-- The 59.99s limit should then be reached after around 959 900 ns.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity simple_sim is

end simple_sim;

architecture behavior of simple_sim is

   -- Constants ----------------------------------------------------------------

   constant display_value_0: std_logic_vector(6 downto 0) := B"0000001";

   constant display_value_1: std_logic_vector(6 downto 0) := B"1001111";

   constant display_value_2: std_logic_vector(6 downto 0) := B"0010010";

   constant display_value_3: std_logic_vector(6 downto 0) := B"0000110";

   constant display_value_4: std_logic_vector(6 downto 0) := B"1001100";

   constant display_value_5: std_logic_vector(6 downto 0) := B"0100100";

   constant display_value_6: std_logic_vector(6 downto 0) := B"0100000";

   constant display_value_7: std_logic_vector(6 downto 0) := B"0001111";

   constant display_value_8: std_logic_vector(6 downto 0) := B"0000000";

   constant display_value_9: std_logic_vector(6 downto 0) := B"0000100";

   constant display_value_error: std_logic_vector(6 downto 0) := B"0110000";

   constant miniclock_period : time := 20 ns;

   -- Signals ------------------------------------------------------------------

   ---- Inputs -----------------------------------------------------------------

   signal CK_50MHz:        std_logic := '0';

   signal reset:           std_logic := '0';

   signal BP_RAZ:          std_logic := '0';

   signal BP_START_STOP:   std_logic := '0';

 	---- Outputs ----------------------------------------------------------------

   signal Display:   std_logic_vector(6 downto 0);

   signal AN:        std_logic_vector(3 downto 0);

   -- Natural representation of Display. 10 means "error".

   signal Display_N: natural range 0 to 10;

   -- Components ---------------------------------------------------------------

   component best_chronometer_ever is

      port

      (

         i_clock:       in std_logic;

         i_reset:       in std_logic;

         i_start_bp:    in std_logic;

         i_raz_bp:      in std_logic;

         o_display:     out std_logic_vector (6 downto 0);

         o_an:          out std_logic_vector (3 downto 0)

      );

   end component;

   -- Functions ----------------------------------------------------------------

   function display_value_to_numeral (D: std_logic_vector(6 downto 0))

      return natural is

   begin

      case D is

         when display_value_0 => return 0;

         when display_value_1 => return 1;

         when display_value_2 => return 2;

         when display_value_3 => return 3;

         when display_value_4 => return 4;

         when display_value_5 => return 5;

         when display_value_6 => return 6;

         when display_value_7 => return 7;

         when display_value_8 => return 8;

         when display_value_9 => return 9;

         when others => return 10;

      end case;

   end display_value_to_numeral;

begin

   -- Unit Under Test ----------------------------------------------------------

   uut: best_chronometer_ever

   port map

   (

      i_clock => CK_50MHZ,

      i_reset => reset,

      i_start_bp => BP_START_STOP,

      i_raz_bp => BP_RAZ,

      o_display => Display,

      o_an => AN

   );

   Display_N <= display_value_to_numeral(Display);

   -- Clock Process ------------------------------------------------------------

   miniclock_process: process

   begin

      CK_50MHz <= '0';

      wait for (miniclock_period / 2);

      CK_50MHz <= '1';

      wait for (miniclock_period / 2);

   end process;

   -- Stimulus Process ---------------------------------------------------------

   stim_proc: process

   begin

      reset         <= '1';

      wait for 50 ns;

      reset         <= '0';

      wait for 50 ns;

      BP_START_STOP <= '0';

      BP_RAZ <= '0';

      wait for 100 ns;

      BP_START_STOP <= '1';

      wait for 100 ns;

      BP_START_STOP <= '0';

      wait for 10000 ns;

      BP_START_STOP <= '1';

      wait for 100 ns;

      BP_START_STOP <= '0';

      wait for 400 ns;

      BP_RAZ <= '1';

      wait for 100 ns;

      BP_RAZ <= '0';

      wait for 400 ns;

      BP_START_STOP <= '1';

      wait for 100 ns;

      BP_START_STOP <= '0';

     assert false report "End of Test" severity note;

     wait;

   end process;

end;