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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue50 / idct.d / sync_ram.vhd @ 2051e520

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-- Simple generic RAM Model
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--
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-- +-----------------------------+
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-- |    Copyright 2008 DOULOS    |
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-- |   designer :  JK            |
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-- +-----------------------------+
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sync_ram is
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  port (
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    clock   : in  std_logic;
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    we      : in  std_logic;
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    address : in  std_logic_vector;
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    datain  : in  std_logic_vector;
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    dataout : out std_logic_vector
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  );
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end entity sync_ram;
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architecture rtl of sync_ram is
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   type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
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   signal ram : ram_type;
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   signal read_address : std_logic_vector(address'range);
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begin
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  ramproc: process(clock) is
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  begin
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    if rising_edge(clock) then
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      if we = '1' then
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        ram(to_integer(unsigned(address))) <= datain;
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      end if;
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      read_address <= address;
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    end if;
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  end process ramproc;
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  dataout <= ram(to_integer(unsigned(read_address)));
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end architecture rtl;