## lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue50 / idct.d / sub_562.vhd @ 2051e520

History | View | Annotate | Download (800 Bytes)

1 |
library ieee; |
---|---|

2 |
use ieee.std_logic_1164.all; |

3 | |

4 |
library ieee; |

5 |
use ieee.numeric_std.all; |

6 | |

7 |
entity sub_562 is |

8 |
port ( |

9 |
result : out std_logic_vector(31 downto 0); |

10 |
in_a : in std_logic_vector(31 downto 0); |

11 |
in_b : in std_logic_vector(31 downto 0) |

12 |
); |

13 |
end sub_562; |

14 | |

15 |
architecture augh of sub_562 is |

16 | |

17 |
signal carry_inA : std_logic_vector(33 downto 0); |

18 |
signal carry_inB : std_logic_vector(33 downto 0); |

19 |
signal carry_res : std_logic_vector(33 downto 0); |

20 | |

21 |
begin |

22 | |

23 |
-- To handle the CI input, the operation is '0' - CI |

24 |
-- If CI is not present, the operation is '0' - '0' |

25 |
carry_inA <= '0' & in_a & '0'; |

26 |
carry_inB <= '0' & in_b & '0'; |

27 |
-- Compute the result |

28 |
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); |

29 | |

30 |
-- Set the outputs |

31 |
result <= carry_res(32 downto 1); |

32 | |

33 |
end architecture; |