lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue50 / idct.d / input_split1.vhd @ 2051e520
History | View | Annotate | Download (1.78 KB)
1 |
library ieee; |
---|---|
2 |
use ieee.std_logic_1164.all; |
3 |
|
4 |
|
5 |
library ieee; |
6 |
use ieee.numeric_std.all; |
7 |
|
8 |
entity input_split1 is |
9 |
port ( |
10 |
wa0_data : in std_logic_vector(31 downto 0); |
11 |
wa0_addr : in std_logic_vector(4 downto 0); |
12 |
ra0_data : out std_logic_vector(31 downto 0); |
13 |
ra0_addr : in std_logic_vector(4 downto 0); |
14 |
wa0_en : in std_logic; |
15 |
ra1_data : out std_logic_vector(31 downto 0); |
16 |
ra1_addr : in std_logic_vector(4 downto 0); |
17 |
ra2_data : out std_logic_vector(31 downto 0); |
18 |
ra2_addr : in std_logic_vector(4 downto 0); |
19 |
ra3_data : out std_logic_vector(31 downto 0); |
20 |
ra3_addr : in std_logic_vector(4 downto 0); |
21 |
clk : in std_logic |
22 |
); |
23 |
end input_split1; |
24 |
architecture augh of input_split1 is |
25 |
|
26 |
-- Embedded RAM |
27 |
|
28 |
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); |
29 |
signal ram : ram_type := (others => (others => '0')); |
30 |
|
31 |
|
32 |
-- Little utility functions to make VHDL syntactically correct |
33 |
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. |
34 |
-- This happens when accessing arrays with <= 2 cells, for example. |
35 |
|
36 |
function to_integer(B: std_logic) return integer is |
37 |
variable V: std_logic_vector(0 to 0); |
38 |
begin |
39 |
V(0) := B; |
40 |
return to_integer(unsigned(V)); |
41 |
end; |
42 |
|
43 |
function to_integer(V: std_logic_vector) return integer is |
44 |
begin |
45 |
return to_integer(unsigned(V)); |
46 |
end; |
47 |
|
48 |
begin |
49 |
|
50 |
-- Sequential process |
51 |
-- It handles the Writes |
52 |
|
53 |
process (clk) |
54 |
begin |
55 |
if rising_edge(clk) then |
56 |
|
57 |
-- Write to the RAM |
58 |
-- Note: there should be only one port. |
59 |
|
60 |
if wa0_en = '1' then |
61 |
ram( to_integer(wa0_addr) ) <= wa0_data; |
62 |
end if; |
63 |
|
64 |
end if; |
65 |
end process; |
66 |
|
67 |
-- The Read side (the outputs) |
68 |
|
69 |
ra0_data <= ram( to_integer(ra0_addr) ); |
70 |
ra3_data <= ram( to_integer(ra3_addr) ); |
71 |
ra1_data <= ram( to_integer(ra1_addr) ); |
72 |
ra2_data <= ram( to_integer(ra2_addr) ); |
73 |
|
74 |
end architecture; |