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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue424 / testCaseGood.json @ 2051e520

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "testCaseGood"], "ports" : [{
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          "names" : [["IDENTIFIER", "outPad"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "inPad"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "3"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "behavioral"], "entity" : ["IDENTIFIER", "testCaseGood"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "subBlock"], "ports" : [{
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              "names" : [["IDENTIFIER", "outPort"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "inPort"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                  "ranges" : [["RANGE_WITH_DIRECTION", {
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                    "direction" : "downto", "from" : ["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CONSTANT_VALUE", {
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                          "value" : ["CST_LITERAL", "3"]}
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                        ]]}
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                      ]]}
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                    ], "_to" : ["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["CONSTANT_VALUE", {
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                          "value" : ["CST_LITERAL", "0"]}
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                        ]]}
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                      ]]}
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                    ]}
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                  ]]}
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                ]}
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              }
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            ]}
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "xsubBlock"], "inst_unit" : ["SIMPLE_NAME", "subBlock"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "outPort"], "actual_designator" : ["SIMPLE_NAME", "outPad"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "inPort"], "actual_designator" : ["SIMPLE_NAME", "inPad"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }