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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue424 / subBlock.vhd @ 2051e520

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library ieee;
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use ieee.std_logic_1164.all;
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entity subBlock is
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    port (outPort : out std_logic;
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          inPort  : in  std_logic_vector(3 downto 0)
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          );
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end entity subBlock;
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architecture behavioral of subBlock is
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begin
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    outPort <= inPort(0);
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end architecture behavioral;