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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue301 / src / traceback.vhd @ 2051e520

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--!
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--! Copyright (C) 2011 - 2014 Creonic GmbH
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--!
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--! @file
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--! @brief  Traceback unit for a viterbi decoder
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--! @author Markus Fehrenz
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--! @date   2011/07/11
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--!
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--! @details The traceback unit only processes a data stream.
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--! There is no knowledge about the decoder configuration.
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--! The information about acquisition and window lengths is received from ram control.
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--!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library dec_viterbi;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param_derived.all;
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entity trellis_traceback is
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	port(
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		-- general signals
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		clk : in std_logic;
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		rst : in std_logic;
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		s_axis_input_tvalid       : in  std_logic;
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		s_axis_input_tdata        : in  std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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		s_axis_input_tlast        : in  std_logic;
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		s_axis_input_tready       : out std_logic;
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		s_axis_input_window_tuser : in  std_logic;
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		s_axis_input_last_tuser   : in  std_logic;
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		m_axis_output_tvalid     : out std_logic;
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		m_axis_output_tdata      : out std_logic;
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		m_axis_output_tlast      : out std_logic;
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		m_axis_output_last_tuser : out std_logic;
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		m_axis_output_tready     : in  std_logic
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	);
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end entity trellis_traceback;
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architecture rtl of trellis_traceback is
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	signal current_node               : unsigned(BW_TRELLIS_STATES - 1 downto 0);
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	signal m_axis_output_tvalid_int   : std_logic;
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	signal s_axis_input_tready_int    : std_logic;
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begin
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	s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' or m_axis_output_tvalid_int = '0' else
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	                           '0';
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	s_axis_input_tready <= s_axis_input_tready_int;
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	m_axis_output_tvalid <= m_axis_output_tvalid_int;
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	-- Traceback the ACS local path decisions and output the resulting global path.
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	pr_traceback : process(clk) is
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	begin
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	if rising_edge(clk) then
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		if rst = '1' then
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			m_axis_output_tvalid_int   <= '0';
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			m_axis_output_tdata        <= '0';
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			m_axis_output_tlast        <= '0';
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			m_axis_output_last_tuser   <= '0';
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			current_node               <= (others => '0');
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		else
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			if m_axis_output_tready = '1' then	
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				m_axis_output_tvalid_int <= '0';
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			end if;
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			-- calculate the decoded bit with an shift register
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			if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
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				m_axis_output_tlast      <= s_axis_input_tlast;
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				m_axis_output_last_tuser <= s_axis_input_last_tuser;
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				-- handle tvalid output signal
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				if s_axis_input_window_tuser = '1' then
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					m_axis_output_tvalid_int <= '1';
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					m_axis_output_tdata <= current_node(BW_TRELLIS_STATES - 1);
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				end if;
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				-- last value of current window?
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				if s_axis_input_last_tuser = '1' then
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					current_node <= to_unsigned(0, BW_TRELLIS_STATES);
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				else
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					current_node <= current_node(BW_TRELLIS_STATES - 2 downto 0)
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					                & s_axis_input_tdata(to_integer(current_node(BW_TRELLIS_STATES - 1 downto 0)));
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				end if;
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			end if;
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		end if;
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	end if;
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	end process pr_traceback;
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end architecture rtl;