lustrectests / vhdl_json / vhdl_files / 2exportOK / ghdl / ghdl / testsuite / gna / issue301 / packages / pkg_components.vhd @ 2051e520
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! 

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! Copyright (C) 2011  2014 Creonic GmbH 
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! 
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! This file is part of the Creonic Viterbi Decoder, which is distributed 
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! under the terms of the GNU General Public License version 2. 
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! 
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! @file 
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! @brief Component declarations for Viterbi decoder 
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! @author Markus Fehrenz 
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! @date 2011/04/07 
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! 
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! 
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library ieee; 
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use ieee.std_logic_1164.all; 
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use ieee.numeric_std.all; 
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library dec_viterbi; 
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use dec_viterbi.pkg_param.all; 
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use dec_viterbi.pkg_param_derived.all; 
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use dec_viterbi.pkg_types.all; 
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package pkg_components is 
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component axi4s_buffer is 
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generic ( 
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DATA_WIDTH : natural := 1 
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); 
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port ( 
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clk : in std_logic; 
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rst : in std_logic; 
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input : in std_logic_vector(DATA_WIDTH  1 downto 0); 
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input_valid : in std_logic; 
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input_last : in std_logic; 
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input_accept : out std_logic; 
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output : out std_logic_vector(DATA_WIDTH  1 downto 0); 
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output_valid : out std_logic; 
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output_last : out std_logic; 
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output_accept : in std_logic 
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); 
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end component axi4s_buffer; 
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component branch_distance is 
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generic( 
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EDGE_WEIGHT : in std_logic_vector(NUMBER_PARITY_BITS  1 downto 0) 
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); 
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port( 
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clk : in std_logic; 
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rst : in std_logic; 
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s_axis_input_tvalid : in std_logic; 
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s_axis_input_tdata : in t_input_block; 
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s_axis_input_tlast : in std_logic; 
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s_axis_input_tready : out std_logic; 
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m_axis_output_tvalid : out std_logic; 
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m_axis_output_tdata : out std_logic_vector(BW_BRANCH_RESULT  1 downto 0); 
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m_axis_output_tlast : out std_logic; 
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m_axis_output_tready : in std_logic 
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); 
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end component branch_distance; 
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component acs is 
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generic( 
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initialize_value : in signed(BW_MAX_PROBABILITY  1 downto 0) 
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); 
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port( 
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clk : in std_logic; 
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rst : in std_logic; 
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s_axis_inbranch_tvalid : in std_logic; 
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s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT  1 downto 0); 
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s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT  1 downto 0); 
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s_axis_inbranch_tlast : in std_logic; 
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s_axis_inbranch_tready : out std_logic; 
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s_axis_inprev_tvalid : in std_logic; 
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s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY  1 downto 0); 
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s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY  1 downto 0); 
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s_axis_inprev_tready : out std_logic; 
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m_axis_outprob_tvalid : out std_logic; 
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m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY  1 downto 0); 
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m_axis_outprob_tready : in std_logic; 
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m_axis_outdec_tvalid : out std_logic; 
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m_axis_outdec_tdata : out std_logic; 
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m_axis_outdec_tlast : out std_logic; 
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m_axis_outdec_tready : in std_logic 
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); 
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end component acs; 
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component ram_ctrl is 
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port( 
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clk : in std_logic; 
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rst : in std_logic; 
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s_axis_input_tvalid : in std_logic; 
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s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES  1 downto 0); 
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s_axis_input_tlast : in std_logic; 
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s_axis_input_tready : out std_logic; 
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m_axis_output_tvalid : out std_logic_vector(1 downto 0); 
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m_axis_output_tdata : out t_ram_rd_data; 
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m_axis_output_tlast : out std_logic_vector(1 downto 0); 
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m_axis_output_tready : in std_logic_vector(1 downto 0); 
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m_axis_output_window_tuser : out std_logic_vector(1 downto 0); 
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m_axis_output_last_tuser : out std_logic_vector(1 downto 0); 
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s_axis_ctrl_tvalid : in std_logic; 
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s_axis_ctrl_tdata : in std_logic_vector(31 downto 0); 
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s_axis_ctrl_tready : out std_logic 
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); 
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end component ram_ctrl; 
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component generic_sp_ram is 
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generic( 
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DISTR_RAM : boolean; 
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WORDS : integer; 
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BITWIDTH : integer 
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); 
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port( 
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clk : in std_logic; 
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rst : in std_logic; 
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wen : in std_logic; 
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en : in std_logic; 
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a : in std_logic_vector(BW_MAX_WINDOW_LENGTH  1 downto 0); 
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d : in std_logic_vector(BITWIDTH  1 downto 0 ); 
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q : out std_logic_vector(BITWIDTH  1 downto 0) 
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); 
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end component generic_sp_ram; 
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component trellis_traceback is 
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port( 
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clk : in std_logic; 
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rst : in std_logic; 
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s_axis_input_tvalid : in std_logic; 
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s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES  1 downto 0); 
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s_axis_input_tlast : in std_logic; 
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s_axis_input_tready : out std_logic; 
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s_axis_input_window_tuser : in std_logic; 
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s_axis_input_last_tuser : in std_logic; 
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m_axis_output_tvalid : out std_logic; 
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m_axis_output_tdata : out std_logic; 
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m_axis_output_tlast : out std_logic; 
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m_axis_output_last_tuser : out std_logic; 
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m_axis_output_tready : in std_logic 
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); 
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end component trellis_traceback; 
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component reorder is 
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port( 
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clk : in std_logic; 
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rst : in std_logic; 
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s_axis_input_tvalid : in std_logic; 
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s_axis_input_tdata : in std_logic; 
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s_axis_input_tlast : in std_logic; 
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s_axis_input_last_tuser : in std_logic; 
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s_axis_input_tready : out std_logic; 
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m_axis_output_tvalid : out std_logic; 
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m_axis_output_tdata : out std_logic; 
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m_axis_output_tlast : out std_logic; 
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m_axis_output_last_tuser : out std_logic; 
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m_axis_output_tready : in std_logic 
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); 
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end component reorder; 
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component recursionx is 
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port( 
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clk : in std_logic; 
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rst : in std_logic; 
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s_axis_input_tvalid : in std_logic; 
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s_axis_input_tdata : in std_logic; 
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s_axis_input_tlast : in std_logic; 
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s_axis_input_tready : out std_logic; 
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m_axis_output_tvalid : out std_logic; 
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m_axis_output_tdata : out std_logic; 
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m_axis_output_tlast : out std_logic; 
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m_axis_output_tready : in std_logic 
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); 
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end component recursionx; 
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end package pkg_components; 