Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue283 / bar.vhd @ 2051e520

History | View | Annotate | Download (245 Bytes)

1
library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
3
use ieee.numeric_std.all;
4

    
5
entity Bar is
6
  port (
7
    a : std_logic
8
  );
9
end entity Bar;
10

    
11
architecture RTL of Bar is
12

    
13
  signal s_test : std_logic_vector(3 downto 0) := "1111";
14

    
15
begin
16

    
17
end architecture;