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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / deb585748 / 585748_deb.vhd @ 2051e520

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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb_test is end;
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architecture arch_tb of tb_test is
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--   signal reset_s, clk_s : std_logic;
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   signal i_s : integer := -1;
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--   signal j_s : integer := -2;
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   -- Here, as it should, an error will be raised during compilation
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--   signal u_s : unsigned(7 downto 0) := to_unsigned(-1, 8);
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   --
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   signal v_s : unsigned(7 downto 0);
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--   signal w_s : unsigned(7 downto 0);
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begin
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   -- Here, as it should, a bound check failure will be raised during simulation
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--   w_s <= to_unsigned(j_s, 8);
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   --
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   -- Here it won't have any error during simulation, but it should
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   v_s <= to_unsigned(i_s, 8);
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   --
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end architecture arch_tb;