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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug20597 / 20597.vhd @ 2051e520

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library ieee;
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use ieee.std_logic_1164.all;
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entity e is
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end entity e;
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architecture a of e is
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signal operator_for_cmp : std_logic_vector(7 downto 0) := (others => 'X');
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begin
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process (operator_for_cmp) is
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begin
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   case operator_for_cmp is
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	when "00000000" =>
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		null;
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	when "00000001" =>
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		null;
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	when "00000002" => -- Me being stupid
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		null;
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	when "00000003" => --Again
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      when others => null;
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   end case;
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end process;
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end architecture;