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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug16782 / bug.vhd @ 2051e520

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entity bug is end entity;
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architecture arch of bug is
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    component comp is port(a :in bit_vector); end component;
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    constant DATAPATH :natural := 16;
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    signal a :bit_vector(DATAPATH-1 downto 0);
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begin
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    i_comp: comp port map(a);
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end architecture;
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entity comp is port(a :in bit_vector); end entity;
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architecture arch of comp is
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    constant DATAPATH :natural := a'length;
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    signal state :natural;
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    signal tmp   :bit_vector(31 downto 0);
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begin
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    process(a) begin
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        case DATAPATH is
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        when 8=>
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            case state is
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                when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
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                when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
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-- When DATAPATH>10 this range violates bounds, but this code should not be reached because "case DATAPATH is when 8=>"
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                when 2=> tmp(3*DATAPATH-1 downto 2*DATAPATH)<=a;
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                when 3=> tmp(4*DATAPATH-1 downto 3*DATAPATH)<=a;
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                when others=>
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            end case;
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        when 16=>
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            case state is
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                when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
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                when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
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                when others=>
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            end case;
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        when others=>
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        end case;
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    end process;
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end architecture;