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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug040 / sub_205.vhd @ 2051e520

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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity sub_205 is
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	port (
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		gt : out std_logic;
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		ge : out std_logic;
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		lt : out std_logic;
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		le : out std_logic;
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		output : out std_logic_vector(40 downto 0);
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		sign : in  std_logic;
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		in_b : in  std_logic_vector(40 downto 0);
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		in_a : in  std_logic_vector(40 downto 0)
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	);
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end sub_205;
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architecture augh of sub_205 is
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	signal carry_inA : std_logic_vector(42 downto 0);
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	signal carry_inB : std_logic_vector(42 downto 0);
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	signal carry_res : std_logic_vector(42 downto 0);
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	-- Signals to generate the comparison outputs
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	signal msb_abr  : std_logic_vector(2 downto 0);
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	signal tmp_sign : std_logic;
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	signal tmp_eq   : std_logic;
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	signal tmp_le   : std_logic;
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	signal tmp_ge   : std_logic;
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begin
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	-- To handle the CI input, the operation is '0' - CI
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	-- If CI is not present, the operation is '0' - '0'
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	carry_inA <= '0' & in_a & '0';
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	carry_inB <= '0' & in_b & '0';
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	-- Compute the result
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	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
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	-- Set the outputs
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	output <= carry_res(41 downto 1);
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	-- Other comparison outputs
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	-- Temporary signals
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	msb_abr <= in_a(40) & in_b(40) & carry_res(41);
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	tmp_sign <= sign;
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	tmp_eq  <= '1' when in_a = in_b else '0';
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	tmp_le <=
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		tmp_eq when msb_abr = "000" or msb_abr = "110" else
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		'1' when msb_abr = "001" or msb_abr = "111" else
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		'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
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		'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
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		'0';
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	tmp_ge <=
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		'1' when msb_abr = "000" or msb_abr = "110" else
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		'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
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		'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
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		'0';
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	gt <= not(tmp_le);
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	ge <= tmp_ge;
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	lt <= not(tmp_ge);
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	le <= tmp_le;
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end architecture;