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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug040 / mul_209.vhd @ 2051e520

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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity mul_209 is
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	port (
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		output : out std_logic_vector(40 downto 0);
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		in_b : in  std_logic_vector(31 downto 0);
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		in_a : in  std_logic_vector(31 downto 0)
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	);
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end mul_209;
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architecture augh of mul_209 is
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	signal tmp_res : signed(63 downto 0);
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begin
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	-- The actual multiplication
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	tmp_res <= signed(in_a) * signed(in_b);
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	-- Set the output
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	output <= std_logic_vector(tmp_res(40 downto 0));
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end architecture;