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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / testcases / latches.json @ 2051e520

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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "IEEE"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "IEEE"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "latches"], "ports" : [{
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          "names" : [["IDENTIFIER", "i_clock"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "i_reset"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "i_a"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "i_b"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "i_c"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "o_a"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "o_b"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "o_c"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "Behavioral"], "entity" : ["IDENTIFIER", "latches"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "latch_0"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
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          "active_sigs" : [["SIMPLE_NAME", "i_reset"], ["SIMPLE_NAME", "i_a"], ["SIMPLE_NAME", "i_b"]], "PROCESS_STATEMENT_PART" : [["IF_STATEMENT", {
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            "if_cases" : [{
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              "if_cond" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "id" : "=", "args" : [["EXPRESSION", {
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                          "args" : [["EXPRESSION", {
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                            "args" : [["EXPRESSION", {
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                              "args" : [["CALL", ["SIMPLE_NAME", "i_reset"]]]}
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                            ]]}
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                          ]]}
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                        ], ["EXPRESSION", {
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                          "args" : [["EXPRESSION", {
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                            "args" : [["EXPRESSION", {
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                              "args" : [["CONSTANT_VALUE", {
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                                "value" : ["CST_LITERAL", "'1'"]}
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                              ]]}
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                            ]]}
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                          ]]}
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                        ]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
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                "lhs" : ["SIMPLE_NAME", "latch_0"], "rhs" : [{
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                  "value" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["EXPRESSION", {
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                          "args" : [["CONSTANT_VALUE", {
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                            "value" : ["CST_LITERAL", "'0'"]}
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                          ]]}
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                        ]]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]}
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              ]]}
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            , {
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              "if_cond" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "id" : "=", "args" : [["EXPRESSION", {
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                          "args" : [["EXPRESSION", {
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                            "args" : [["EXPRESSION", {
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                              "args" : [["CALL", ["SIMPLE_NAME", "i_b"]]]}
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                            ]]}
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                          ]]}
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                        ], ["EXPRESSION", {
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                          "args" : [["EXPRESSION", {
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                            "args" : [["EXPRESSION", {
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                              "args" : [["CONSTANT_VALUE", {
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                                "value" : ["CST_LITERAL", "'1'"]}
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                              ]]}
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                            ]]}
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                          ]]}
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                        ]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], "if_block" : [["SIGNAL_ASSIGNMENT_STATEMENT", {
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                "lhs" : ["SIMPLE_NAME", "latch_0"], "rhs" : [{
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                  "value" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["EXPRESSION", {
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                        "args" : [["EXPRESSION", {
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                          "args" : [["CALL", ["SIMPLE_NAME", "i_a"]]]}
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                        ]]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]}
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              ]]}
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            ]}
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          ]]}
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        ]]}
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      ]}
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    ]}
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  }