Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / testcases / computational.vhd @ 2051e520

History | View | Annotate | Download (965 Bytes)

1
library IEEE;
2

    
3
use IEEE.std_logic_1164.ALL;
4

    
5
entity computational is
6
   port
7
   (
8
      i_clock: in std_logic;
9
      i_reset: in std_logic;
10
      i_a:     in std_logic;
11
      i_b:     in std_logic;
12
      i_c:     in std_logic;
13
      o_a:     out std_logic;
14
      o_b:     out std_logic;
15
      o_c:     out std_logic
16
   );
17
end entity computational;
18

    
19
architecture Behavioral of computational is
20
begin
21

    
22
   process (i_a, i_b, i_c)
23
   begin
24
      o_a <= i_b;
25
      if (i_a = '1')
26
      then
27
         o_a <= i_c;
28
      end if;
29
   end process;
30

    
31
   process (i_a, i_b, i_c)
32
   begin
33
      if (i_a = '1')
34
      then
35
         o_a <= i_c;
36
      else
37
         o_a <= i_b;
38
      end if;
39
   end process;
40

    
41
   process (i_c)
42
   begin
43
      o_a <= i_a;
44
      o_a <= i_b;
45
      o_a <= i_c;
46
   end process;
47

    
48
   process (i_c)
49
   begin
50
      if (i_a = '1')
51
      then
52
         o_a <= i_c;
53
      else
54
         o_a <= i_b;
55
      end if;
56
      o_a <= i_c;
57
   end process;
58

    
59
end architecture;