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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / best-chronometer-ever / src / crossdomain_sync.vhd @ 2051e520

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library IEEE;
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use IEEE.std_logic_1164.all;
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entity crossdomain_sync is
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   port
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   (
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      i_clock:    in std_logic;  -- System clock.
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      i_reset:    in std_logic;  -- System reset.
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      i_signal:   in std_logic;  -- Asynchronous signal.
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      o_signal:   out std_logic  -- Synchronous signal.
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   );
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end crossdomain_sync;
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architecture Behavioral of crossdomain_sync is
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   signal signal_r1: std_logic;
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   signal signal_r2: std_logic;
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begin
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   P_R1_HANDLER: process (i_clock, i_reset)
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   begin
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      if (i_reset = '1')
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      then
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         signal_r1 <= '0';
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      else
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         if (rising_edge(i_clock))
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         then
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            signal_r1 <= i_signal;
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         end if;
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      end if;
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   end process;
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   P_R2_HANDLER: process (i_clock, i_reset)
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   begin
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      if (i_reset = '1')
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      then
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         signal_r2 <= '0';
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      else
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         if (rising_edge(i_clock))
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         then
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            signal_r2 <= i_signal;
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         end if;
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      end if;
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   end process;
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   o_signal <= signal_r2;
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end;