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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / best-chronometer-ever / src / best_chronometer_ever.vhd @ 2051e520

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--------------------------------------------------------------------------------
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-- BEST CHRONOMETER EVER -------------------------------------------------------
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--------------------------------------------------------------------------------
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library IEEE;
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-- Required by the use of "std_logic_vector".
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use IEEE.STD_LOGIC_1164.ALL;
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entity best_chronometer_ever is
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   port
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   (
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      i_clock:       in std_logic;
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      i_reset:       in std_logic;
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      i_start_bp:    in std_logic;
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      i_raz_bp:      in std_logic;
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      o_display:     out std_logic_vector (6 downto 0);
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      o_an:          out std_logic_vector (3 downto 0)
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   );
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end best_chronometer_ever;
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architecture Behavioral of best_chronometer_ever is
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   -- Signals ------------------------------------------------------------------
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   signal new_centisecond: std_logic;
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   signal raz:             std_logic;
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   signal enable:          std_logic;
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   signal limit_reached:   std_logic;
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   signal synced_start_bp: std_logic;
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   signal synced_raz_bp:   std_logic;
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   signal numeral_display: natural range 0 to 9;
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   signal curr_0001_time:  natural range 0 to 9;
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   signal curr_0010_time:  natural range 0 to 9;
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   signal curr_0100_time:  natural range 0 to 9;
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   signal curr_1000_time:  natural range 0 to 5;
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   -- Components ---------------------------------------------------------------
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   component centisecond_timer is
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      generic
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      (
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      ---- For implementation:
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      --  g_clock_cycle_per_centisecond: natural := 500000
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      ---- For testing, we recommend using:
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          g_clock_cycle_per_centisecond: natural := 8
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      );
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      port
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      (
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         i_clock:           in std_logic; -- System clock.
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         i_reset:           in std_logic; -- System reset.
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         i_raz:             in std_logic; -- User triggered raz.
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         i_enable:          in std_logic; -- Time is passing.
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         o_new_centisecond: out std_logic -- Centisecond pulse.
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      );
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   end component;
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   component crossdomain_sync is
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      port
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      (
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         i_clock:    in std_logic;  -- System clock.
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         i_reset:    in std_logic;  -- System reset.
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         i_signal:   in std_logic;  -- Asynchronous signal.
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         o_signal:   out std_logic  -- Synchronous signal.
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      );
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   end component;
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   component display_manager is
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      generic
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      (
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      ---- For implementation:
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      --  g_clock_cycle_per_display: natural := 125000
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      ---- For testing, we recommend using:
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          g_clock_cycle_per_display: natural := 2
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      );
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      port
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      (
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         i_clock:          in std_logic;                       -- System clock.
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         i_reset:          in std_logic;                       -- System reset.
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         i_curr_0001_time: in natural range 0 to 9;            -- Centiseconds
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         i_curr_0010_time: in natural range 0 to 9;            -- deciseconds
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         i_curr_0100_time: in natural range 0 to 9;            -- seconds
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         i_curr_1000_time: in natural range 0 to 5;            -- decaseconds
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         o_display:        out natural range 0 to 9;           -- number on display
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         o_an:             out std_logic_vector (3 downto 0)   -- selected display
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      );
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   end component;
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   component numeral_to_display is
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      generic
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      (
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      -- To be moved into a converter.
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         g_display_value_0:         std_logic_vector(6 downto 0) := B"0000001";
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         g_display_value_1:         std_logic_vector(6 downto 0) := B"1001111";
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         g_display_value_2:         std_logic_vector(6 downto 0) := B"0010010";
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         g_display_value_3:         std_logic_vector(6 downto 0) := B"0000110";
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         g_display_value_4:         std_logic_vector(6 downto 0) := B"1001100";
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         g_display_value_5:         std_logic_vector(6 downto 0) := B"0100100";
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         g_display_value_6:         std_logic_vector(6 downto 0) := B"0100000";
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         g_display_value_7:         std_logic_vector(6 downto 0) := B"0001111";
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         g_display_value_8:         std_logic_vector(6 downto 0) := B"0000000";
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         g_display_value_9:         std_logic_vector(6 downto 0) := B"0000100";
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         g_display_value_error:     std_logic_vector(6 downto 0) := B"0110000"
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      );
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      port
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      (
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         i_numeral_time: in natural range 0 to 9;     -- numeral input
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         o_display:  out std_logic_vector(6 downto 0) -- display output
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      );
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   end component;
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   component time_wizard is
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      port
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      (
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         i_clock:             in std_logic;
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         i_reset:             in std_logic;
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         i_raz:               in std_logic;
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         i_new_centisecond:   in std_logic;
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         o_limit_reached:     out std_logic;
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         o_curr_0001_time:    out natural range 0 to 9;
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         o_curr_0010_time:    out natural range 0 to 9;
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         o_curr_0100_time:    out natural range 0 to 9;
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         o_curr_1000_time:    out natural range 0 to 5
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      );
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   end component;
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   component user_handler is
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      port
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      (
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         i_clock:             in std_logic;  -- System's clock.
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         i_reset:             in std_logic;  -- System reset.
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         i_synced_start_btn:  in std_logic;  -- User input. Synchronized.
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         i_synced_raz_btn:    in std_logic;  -- User input. Synchronized.
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         i_limit_reached:     in std_logic;  -- Time Wizard has reached limit.
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         o_enable:            out std_logic; -- Enable time passing.
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         o_raz:               out std_logic  -- Reset system.
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      );
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   end component;
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begin
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   START_BP_SYNCHRONIZER: crossdomain_sync port map
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   (
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      i_clock => i_clock,
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      i_reset => i_reset,
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      i_signal => i_start_bp,
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      o_signal => synced_start_bp
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   );
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   RAZ_BP_SYNCHRONIZER: crossdomain_sync port map
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   (
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      i_clock => i_clock,
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      i_reset => i_reset,
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      i_signal => i_raz_bp,
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      o_signal => synced_raz_bp
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   );
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   CNTSCD_TM: centisecond_timer port map
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   (
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      i_clock => i_clock,
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      i_reset => i_reset,
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      i_raz => raz,
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      i_enable => enable,
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      o_new_centisecond => new_centisecond
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   );
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   DSPLY_MGR: display_manager port map
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   (
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      i_clock => i_clock,
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      i_reset => i_reset,
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      i_curr_0001_time => curr_0001_time,
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      i_curr_0010_time => curr_0010_time,
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      i_curr_0100_time => curr_0100_time,
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      i_curr_1000_time => curr_1000_time,
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      o_display => numeral_display,
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      o_an => o_an
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   );
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   DSPLY_TRSLTR: numeral_to_display port map
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   (
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      i_numeral_time => numeral_display,
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      o_display => o_display
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   );
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   TM_WZRD: time_wizard port map
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   (
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      i_clock => i_clock,
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      i_reset => i_reset,
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      i_raz => raz,
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      i_new_centisecond => new_centisecond,
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      o_limit_reached => limit_reached,
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      o_curr_0001_time => curr_0001_time,
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      o_curr_0010_time => curr_0010_time,
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      o_curr_0100_time => curr_0100_time,
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      o_curr_1000_time => curr_1000_time
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   );
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   USR_HNDLR: user_handler port map
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   (
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      i_clock => i_clock,
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      i_reset => i_reset,
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      i_synced_start_btn => synced_start_bp,
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      i_synced_raz_btn => synced_raz_bp,
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      i_limit_reached => limit_reached,
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      o_enable => enable,
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      o_raz => raz
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   );
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end;