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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / STD_04200_good.vhd @ 2051e520

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-- Company   : CNES
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-- Author    : Mickael Carl (CNES)
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-- Copyright : Copyright (c) CNES.
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-- Licensing : GNU GPLv3
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-------------------------------------------------------------------------------------------------
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-- Version         : V1
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-- Version history :
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--    V1 : 2015-04-08 : Mickael Carl (CNES): Creation
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-------------------------------------------------------------------------------------------------
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-- File name          : STD_04200_good.vhd
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-- File Creation date : 2015-04-08
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-- Project name       : VHDL Handbook CNES Edition
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-------------------------------------------------------------------------------------------------
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-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
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-- Description : Handbook exemple: Clock domain crossing handshake based: good example
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--
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-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
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--               demonstrating good practices in VHDL and as such, its design is minimalistic.
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--               It is provided as is, without any warranty.
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--               This example is compliant with the Handbook version 1.
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--
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-------------------------------------------------------------------------------------------------
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-- Naming conventions:
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--
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-- i_Port: Input entity port
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-- o_Port: Output entity port
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-- b_Port: Bidirectional entity port
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-- g_My_Generic: Generic entity port
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--
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-- c_My_Constant: Constant definition
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-- t_My_Type: Custom type definition
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--
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-- My_Signal_n: Active low signal
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-- v_My_Variable: Variable
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-- sm_My_Signal: FSM signal
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-- pkg_Param: Element Param coming from a package
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--
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-- My_Signal_re: Rising edge detection of My_Signal
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-- My_Signal_fe: Falling edge detection of My_Signal
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-- My_Signal_rX: X times registered My_Signal signal
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--
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-- P_Process_Name: Process
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--
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-------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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--CODE
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entity STD_04200_good is
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   generic (g_Width : positive := 4);
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   port (
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      -- A clock domain (Source)
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      i_ClockA     : in  std_logic;     -- First clock signal
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      i_ResetA_n   : in  std_logic;     -- Reset signal
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      i_Data       : in  std_logic_vector(g_Width-1 downto 0);  -- Data from source
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      i_Request    : in  std_logic;     -- Request from source
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      o_Grant      : out std_logic;     -- Acknowledge synced to source
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      -- B clock domain (Destination)
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      i_ClockB     : in  std_logic;     -- Second clock signal
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      i_ResetB_n   : in  std_logic;     -- Reset signal
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      o_Data       : out std_logic_vector(g_Width-1 downto 0);  -- Data to destination
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      o_Request_r2 : out std_logic;     -- Request synced to destination
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      i_Grant      : in  std_logic      -- Acknowledge from destination
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      );
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end STD_04200_good;
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architecture Behavioral of STD_04200_good is
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   signal Request_r1 : std_logic;       -- Request signal registered 1 time
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   signal Request_r2 : std_logic;       -- Request signal registered 2 times
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   signal Grant_r1   : std_logic;       -- Grant signal registered 1 time
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   signal Grant_r2   : std_logic;       -- Grant signal registered 2 times
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begin
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   P_Source_Domain : process(i_ResetA_n, i_ClockA)
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   begin
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      if (i_ResetA_n = '0') then
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         Grant_r1 <= '0';
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         Grant_r2 <= '0';
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      elsif (rising_edge(i_ClockA)) then
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            -- Synchronize i_Grant to i_ClockA domain
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            Grant_r1 <= i_Grant;
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            Grant_r2 <= Grant_r1;
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      end if;
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   end process;
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   P_Destination_Domain : process(i_ResetB_n, i_ClockB)
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   begin
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      if (i_ResetB_n = '0') then
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         Request_r1 <= '0';
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         Request_r2 <= '0';
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      elsif (rising_edge(i_ClockB)) then
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            -- Synchronize i_Request to i_ClockB domain
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            -- Data is valid when Request_r2 is asserted
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            Request_r1 <= i_Request;
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            Request_r2 <= Request_r1;
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      end if;
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   end process;
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   o_Request_r2 <= Request_r2;
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   o_Data       <= i_Data;
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   o_Grant      <= Grant_r2;
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end Behavioral;
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--CODE