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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / STD_02200_bad.vhd @ 2051e520

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--CODE
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-------------------------------------------------------------------------------------------------
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-- Author: Mickael Carl
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-- Date: 2015-04-02
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-------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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--CODE
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entity STD_02200_bad is
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   port (
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      i_Clock   : in  std_logic;        -- Clock signal
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      i_Reset_n : in  std_logic;        -- Reset signal
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      i_D       : in  std_logic;        -- D Flip-Flop input signal
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      o_Q       : out std_logic         -- D Flip-Flop output signal
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      );
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end STD_02200_bad;
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architecture Behavioral of STD_02200_bad is
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   signal Q : std_logic;                -- D Flip-Flop output
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begin
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   -- D FlipFlop process
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   P_FlipFlop : process(i_Clock, i_Reset_n)
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   begin
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      if (i_Reset_n = '0') then
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         Q <= '0';
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      elsif (rising_edge(i_Clock)) then
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            Q <= i_D;
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      end if;
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   end process;
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   o_Q <= Q;
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end Behavioral;