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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / CNE_04900_bad.vhd @ 2051e520

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-- Company   : CNES
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-- Author    : Mickael Carl (CNES)
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-- Copyright : Copyright (c) CNES. 
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-- Licensing : GNU GPLv3
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-- Version         : V1
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-- Version history : 
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--    V1 : 2015-04-17 : Mickael Carl (CNES): Creation
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-- File name          : CNE_04900_bad.vhd
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-- File Creation date : 2015-04-17
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-- Project name       : VHDL Handbook CNES Edition 
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-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
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-- Description : Handbook example: Use of clock signal: bad example
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--
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-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
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--               demonstrating good practices in VHDL and as such, its design is minimalistic.
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--               It is provided as is, without any warranty.
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--               This example is compliant with the Handbook version 1.
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--
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-- Naming conventions: 
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--
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-- i_Port: Input entity port
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-- o_Port: Output entity port
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-- b_Port: Bidirectional entity port
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-- g_My_Generic: Generic entity port
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--
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-- c_My_Constant: Constant definition 
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-- t_My_Type: Custom type definition
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--
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-- My_Signal_n: Active low signal
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-- v_My_Variable: Variable
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-- sm_My_Signal: FSM signal
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-- pkg_Param: Element Param coming from a package
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--
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-- My_Signal_re: Rising edge detection of My_Signal
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-- My_Signal_fe: Falling edge detection of My_Signal
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-- My_Signal_rX: X times registered My_Signal signal
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--
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-- P_Process_Name: Process
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.pkg_HBK.all;
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entity CNE_04900_bad is
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   port  (
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      i_Clock     : in std_logic;   -- Clock signal
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      i_Reset_n   : in std_logic;   -- Reset signal
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      i_Enable    : in std_logic;   -- Enable signal
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      i_D         : in std_logic;   -- D Flip-Flop input signal
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      o_Q         : out std_logic   -- D Flip-Flop output signal
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   );
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end CNE_04900_bad;
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--CODE
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architecture Behavioral of CNE_04900_bad is
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   signal Gated_Clock : std_logic;  -- Gated clock signal
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begin
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   Gated_Clock <= i_Clock and i_Enable;
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   DFF:DFlipFlop
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   port map (
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      i_Clock     => Gated_Clock,
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      i_Reset_n   => i_Reset_n,
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      i_D         => i_D,
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      o_Q         => o_Q,
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      o_Q_n       => open
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   );
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end Behavioral;
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--CODE