Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / CNE_04500_bad.vhd @ 2051e520

History | View | Annotate | Download (3.15 KB)

1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-17 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_04500_bad.vhd
12
-- File Creation date : 2015-04-17
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Reset registers: bad example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

    
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

    
52
--CODE
53
entity CNE_04500_bad is
54
   generic (
55
      g_Width : positive := 4
56
   );
57
   port  (
58
      i_Clock : in std_logic;
59
      i_Reset_n : in std_logic;
60
      i_Data : in std_logic_vector(g_Width-1 downto 0);
61
      o_Sum : out std_logic_vector(g_Width downto 0)
62
   );
63
end CNE_04500_bad;
64

    
65
architecture Behavioral of CNE_04500_bad is
66
   type Data_4_Reg is array (0 to 3) of std_logic_vector(g_Width-1 downto 0);
67
   signal Data_Reg : Data_4_Reg;
68
   signal Sum : std_logic_vector(g_Width downto 0);
69
   signal Sum_r : std_logic_vector(g_Width downto 0);
70
begin
71
   p_Reg:process(i_Reset_n,i_Clock)
72
   begin
73
      if (i_Reset_n='0') then
74
         Data_Reg <= (others => (others => '0'));
75
      elsif (rising_edge(i_Clock)) then
76
            Data_Reg(3) <= Data_Reg(2);
77
            Data_Reg(2) <= Data_Reg(1);
78
            Data_Reg(1) <= Data_Reg(0);
79
            Data_Reg(0) <= i_Data;
80
            Sum_r <= Sum;
81
      end if;
82
   end process;
83
   
84
   Sum <= std_logic_vector(unsigned('0' & Data_Reg(3)) + unsigned('0' & Data_Reg(2)));
85
   o_Sum <= Sum_r;
86
end Behavioral;
87
--CODE