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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / CNE_02000_good.vhd @ 2051e520

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-- Company   : CNES
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-- Author    : Mickael Carl (CNES)
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-- Copyright : Copyright (c) CNES. 
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-- Licensing : GNU GPLv3
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-- Version         : V1
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-- Version history : 
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--    V1 : 2015-04-20 : Mickael Carl (CNES): Creation
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-- File name          : CNE_02000_good.vhd
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-- File Creation date : 2015-04-20
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-- Project name       : VHDL Handbook CNES Edition 
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-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
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-- Description : Handbook example: Identification of Finite State Machine: good example
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--
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-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
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--               demonstrating good practices in VHDL and as such, its design is minimalistic.
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--               It is provided as is, without any warranty.
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--               This example is compliant with the Handbook version 1.
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--
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-------------------------------------------------------------------------------------------------
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-- Naming conventions: 
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--
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-- i_Port: Input entity port
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-- o_Port: Output entity port
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-- b_Port: Bidirectional entity port
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-- g_My_Generic: Generic entity port
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--
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-- c_My_Constant: Constant definition 
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-- t_My_Type: Custom type definition
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--
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-- My_Signal_n: Active low signal
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-- v_My_Variable: Variable
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-- sm_My_Signal: FSM signal
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-- pkg_Param: Element Param coming from a package
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--
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-- My_Signal_re: Rising edge detection of My_Signal
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-- My_Signal_fe: Falling edge detection of My_Signal
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-- My_Signal_rX: X times registered My_Signal signal
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--
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-- P_Process_Name: Process
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--
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-------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity CNE_02000_good is
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   port  (
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      i_Clock     : in std_logic;   -- Clock input
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      i_Reset_n   : in std_logic;   -- Reset input
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      i_Start     : in std_logic;   -- Start counter signal
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      i_Stop      : in std_logic    -- Stop counter signal
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   );
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end CNE_02000_good;
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architecture Behavioral of CNE_02000_good is
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   constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
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--CODE
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   type t_state      is (init, loading, enabled, finished);             -- Enumerated type for state encoding
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   signal sm_State   : t_state;                                         -- State signal
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--CODE
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   signal Raz        : std_logic;                                       -- Load the length value and initialize the counter
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   signal Enable     : std_logic;                                       -- Counter enable signal
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   signal Length     : std_logic_vector(3 downto 0);                    -- Counter length for counting
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   signal End_Count  : std_logic;                                       -- End signal of counter
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begin
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   -- A simple counter with loading length and enable signal
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   Counter:Counter
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   port map (
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      i_Clock     => i_Clock,
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      i_Reset_n   => i_Reset_n,
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      i_Raz       => Raz,
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      i_Enable    => Enable,
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      i_Length    => Length,
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      o_Done      => End_Count
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   );
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   -- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop), 
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   -- load the length value, and wait for it to finish
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   P_FSM:process(i_Reset_n, i_Clock)
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   begin
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      if (i_Reset_n='0') then
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         sm_State <= init;
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      elsif (rising_edge(i_Clock)) then
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            case sm_State is
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               when init => 
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               -- Set the length value
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                  Length <= c_Length;
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                  sm_State <= loading;
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               when loading =>
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               -- Load the counter and initialize it
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                  Raz <= '1';
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                  sm_State <= enabled;
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               when enabled =>
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               -- Start or stop counting depending on inputs until it finishes
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                  Raz <= '0';
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                  if (End_Count='0') then
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                     Enable <= i_Start xor not i_Stop;
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                     sm_State  <= Enabled;
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                  else
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                     Enable <= '0';
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                     sm_State <= finished;
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                  end if;
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               when others =>
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                  sm_State <= init;
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            end case;
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      end if;
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   end process;
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end Behavioral;