Project

General

Profile

Statistics
| Branch: | Tag: | Revision:

lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / CNE_01700_good.vhd @ 2051e520

History | View | Annotate | Download (2.92 KB)

1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01700_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of rising edge detection signal: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

    
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

    
52
--CODE
53
entity CNE_01700_good is
54
   port  (
55
      i_Reset_n   : in std_logic;   -- Reset signal
56
      i_Clock     : in std_logic;   -- Clock signal
57
      i_D         : in std_logic;   -- Signal on which detect edges
58
      o_D_re      : out std_logic   -- Rising edge of i_D
59
   );
60
end CNE_01700_good;
61

    
62
architecture Behavioral of CNE_01700_good is
63
   signal D_r1 : std_logic; -- i_D registered 1 time
64
   signal D_r2 : std_logic; -- i_D registered 2 times
65
begin
66
   -- Rising edge detection process
67
   P_detection: process(i_Reset_n, i_Clock)
68
   begin
69
      if (i_Reset_n='0') then
70
         D_r1 <= '0';
71
         D_r2 <= '0';
72
      elsif (rising_edge(i_Clock)) then
73
            D_r1 <= i_D;
74
            D_r2 <= D_r1;
75
      end if;
76
   end process;
77
   
78
   o_D_re <= D_r1 and not D_r2;
79
end Behavioral;
80
--CODE