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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / CNE_01500_good.vhd @ 2051e520

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-- Company   : CNES
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-- Author    : Mickael Carl (CNES)
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-- Copyright : Copyright (c) CNES. 
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-- Licensing : GNU GPLv3
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-- Version         : V1
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-- Version history : 
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--    V1 : 2015-04-15 : Mickael Carl (CNES): Creation
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-- File name          : CNE_01500_good.vhd
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-- File Creation date : 2015-04-15
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-- Project name       : VHDL Handbook CNES Edition 
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-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
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-- Description : Handbook example: Identification of custom type name: good example
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--
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-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
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--               demonstrating good practices in VHDL and as such, its design is minimalistic.
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--               It is provided as is, without any warranty.
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--               This example is compliant with the Handbook version 1.
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--
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-------------------------------------------------------------------------------------------------
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-- Naming conventions: 
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--
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-- i_Port: Input entity port
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-- o_Port: Output entity port
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-- b_Port: Bidirectional entity port
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-- g_My_Generic: Generic entity port
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--
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-- c_My_Constant: Constant definition 
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-- t_My_Type: Custom type definition
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--
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-- My_Signal_n: Active low signal
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-- v_My_Variable: Variable
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-- sm_My_Signal: FSM signal
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-- pkg_Param: Element Param coming from a package
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--
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-- My_Signal_re: Rising edge detection of My_Signal
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-- My_Signal_fe: Falling edge detection of My_Signal
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-- My_Signal_rX: X times registered My_Signal signal
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--
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-- P_Process_Name: Process
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity CNE_01500_good is
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port  (
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      i_Reset_n   : in std_logic;                     -- Reset signal
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      i_Clock     : in std_logic;                     -- Clock signal
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      i_Addr      : in std_logic_vector(1 downto 0);  -- Address to read from or write to
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      i_Rd        : in std_logic;                     -- Read signal
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      i_Wr        : in std_logic;                     -- Write signal
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      i_Data      : in std_logic;                     -- Incoming data to write
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      o_Data      : out std_logic                     -- Data read
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   );
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end CNE_01500_good;
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--CODE
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architecture Behavioral of CNE_01500_good is
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   type t_register is array (0 to 3) of std_logic; -- Array for signal registration
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   signal D : t_register;                          -- Actual signal
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   signal Data : std_logic;                        -- Module output
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begin
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   -- Describes a simple Register bank with Read and Write signals
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   P_Register_Bank:process(i_Reset_n, i_Clock)
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   begin
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      if (i_Reset_n='0') then
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         D <= (others => '0');
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         Data <= '0';
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      elsif (rising_edge(i_Clock)) then
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            if (i_Rd='1') then
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            -- Read memory
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               Data <= D(to_integer(unsigned(i_Addr)));
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            elsif (i_Wr='1') then
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            -- Write memory
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               D(to_integer(unsigned(i_Addr))) <= i_Data;
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            end if;
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      end if;
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   end process;
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   o_Data <= Data;
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end Behavioral;
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--CODE