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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / cfg / user_handler.vhd @ 2051e520

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library IEEE;
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use IEEE.std_logic_1164.all;
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entity user_handler is
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   port
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   (
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      i_clock:             in std_logic;  -- System's clock.
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      i_reset:             in std_logic;  -- System reset.
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      i_synced_start_btn:  in std_logic;  -- User input. Synchronized.
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      i_synced_raz_btn:    in std_logic;  -- User input. Synchronized.
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      i_limit_reached:     in std_logic;  -- Time Wizard has reached limit.
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      o_enable:            out std_logic; -- Enable time passing.
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      o_raz:               out std_logic  -- Reset system.
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   );
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end user_handler;
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architecture Behavioral of user_handler is
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   -- Previous value of BP_START_STOP (Lustre inspired).
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   signal synced_start_btn_r1: std_logic;
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   -- Remember if we are currently counting time or not.
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   signal time_is_passing: std_logic;
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begin
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   P_ENABLE_TIME: process (i_clock, i_reset)
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   begin
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      if (i_reset = '1')
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      then
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         time_is_passing <= '0';
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      else
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         if (rising_edge(i_clock))
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         then
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            if ((synced_start_btn_r1 = '0') and (i_synced_start_btn = '1'))
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            then
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               time_is_passing <= (not time_is_passing);
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            end if;
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         end if;
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      end if;
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   end process;
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   P_PRE_SYNCED_START_BTN: process (i_clock, i_reset)
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   begin
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      if (i_reset = '1')
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      then
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         synced_start_btn_r1 <= '0';
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      else
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         if (rising_edge(i_clock))
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         then
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            synced_start_btn_r1 <= i_synced_start_btn;
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         end if;
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      end if;
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   end process;
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   o_raz <= (i_synced_raz_btn and time_is_passing);
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   o_enable <= time_is_passing;
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end;