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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue50 / idct.d / pkg_tb.vhd @ 2051e520

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1 2051e520 Arnaud Dieumegard
--test bench written by alban bourge @ tima
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package pkg_tb is
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	--fsm state types
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	type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop);
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	--context descriptor
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	subtype context_t is std_logic_vector(1 downto 0);
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	--argument width and type of fsm instruction
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	constant ARG_WIDTH : integer := 8;
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	subtype argument_t is unsigned(ARG_WIDTH - 1 downto 0);
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	type instruction is 
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		record
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			state       : state_t;
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			context_uut : context_t;
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			arg         : argument_t;
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		end record;
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	--reset instruction
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	constant instr_rst : instruction := (state => Rst, context_uut => (others =>'0'), arg => (others =>'0'));
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	--ram instruction
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	type ram_instruction is
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		record
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			sel     : std_logic;
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			we      : std_logic;
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			addr_up : std_logic;
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			addr_z  : std_logic;
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		end record;
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	constant ram_instr_z : ram_instruction := (sel => '0', we => '0', addr_up => '0', addr_z => '0');
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	--assert unit instruction
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	type assert_instruction is
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		record
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			en_feed  : std_logic;
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			en_check : std_logic;
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		end record;
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	constant assert_instr_z : assert_instruction := (en_feed => '0', en_check => '0');
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	--size of instruction table defined by PC_SIZE i.e. width of program counter
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	constant PC_SIZE : integer := 5;
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	type table_behavior is array (0 to 2**PC_SIZE - 1) of instruction;
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	--constraint fixed by unit under test (augh dependant)
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	--##CONSTRAINTS_START##--
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	subtype stdin_vector is std_logic_vector(31 downto 0);
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	subtype stdout_vector is std_logic_vector(7 downto 0);
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	subtype cp_vector is std_logic_vector(63 downto 0);
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	--##CONSTRAINTS_END##--
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	--assert_uut vector number counter size
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	constant VEC_NO_SIZE : integer := 20;
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end pkg_tb;